With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.

Post-placement temperature reduction techniques / Liu, Wei; Nannarelli, A.; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2010), pp. 634-637. (Intervento presentato al convegno DATE'10: IEEE Designa, Automation and Test in Europe tenutosi a Dresden nel March).

Post-placement temperature reduction techniques

LIU, WEI;CALIMERA, ANDREA;MACII, Enrico;PONCINO, MASSIMO
2010

Abstract

With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.
2010
9783981080162
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2503249
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