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EnglishWith technology scaled to deep submicron regime, temperature and temperature gradient have emerged as important design criteria. Elevated temperatures, spatial and temporal temperature variations and on-chip hotspot not only affect timing in both transistors and interconnects but also degrade circuit reliability. A SPICE simulation based thermal modeling method is proposed in this paper. Experiments on a set of tests show the correlations between functional and spatial hotspots in a circuit implemented in STM 65nm technologies.
On-chip Thermal Modeling Based on SPICE Simulation / Wei L.; Calimera A.; Nannarelli A.; Macii E.; Poncino M.. - ELETTRONICO. - 5953(2010), pp. 66-75. ((Intervento presentato al convegno 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009 tenutosi a Delft (NL) nel September 9-11, 2009 [10.1007/978-3-642-11802-9_11].
| Titolo: | On-chip Thermal Modeling Based on SPICE Simulation | |
| Autori: | ||
| Data di pubblicazione: | 2010 | |
| Rivista: | ||
| Abstract: | With technology scaled to deep submicron regime, temperature and temperature gradient have emerge...d as important design criteria. Elevated temperatures, spatial and temporal temperature variations and on-chip hotspot not only affect timing in both transistors and interconnects but also degrade circuit reliability. A SPICE simulation based thermal modeling method is proposed in this paper. Experiments on a set of tests show the correlations between functional and spatial hotspots in a circuit implemented in STM 65nm technologies. | |
| ISBN: | 9783642118012 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| 2380165.pdf | 2. Post-print / Author's Accepted Manuscript | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2380165
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