Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs

This brief describes a novel integration strategy that aims at bringing adiabatic computation to large scale integration. The proposed design solution, built upon logic primitives packed into regular arrays, the quasi-adiabatic-logic-arrays (QALAs), is well suited not just for today's silicon transistors but also for emerging devices. QALAs are indeed a viable path toward the integration of ultra-low power ICs using devices with a gapless energy spectrum, graphene p-n junctions in particular. The design of QALA circuits is supported by a dedicated RTL-to-device design framework whose kernel consists of a new area/delay-driven logic synthesis and optimization engine. Simulation results conducted on several benchmarks mapped both onto silicon (using 40 nm MOSFETs) and graphene (using electrostatically controlled p-n junctions) show the proposed methodology provides adiabatic logic circuits with a power-delay-product that is one order of magnitude smaller than that of state-of-the-art adiabatic circuits implemented using pass-transistor logic and conventional logic synthesis flows