The memory space taken to host and process large tensor graphs is a limiting factor for embedded ConvNets. Even though many data-driven compression pipelines have proven their efficacy, this work shows there is still room for optimization at the intersection with compute-oriented optimizations. We demonstrate that tensor pruning via weight sparsification can cooperate with a model-agnostic tiling strategy, leading ConvNets towards a new feasible region of the solution space. The collected results show for the first time fast versions of MobileNets deployed at full scale on an ARM M7 core with 512KB of RAM and 2MB of FLASH memory.

On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage / Cipolletta, A.; Calimera, A.. - ELETTRONICO. - (2021), pp. 643-648. ((Intervento presentato al convegno 58th ACM/IEEE Design Automation Conference, DAC 2021 tenutosi a usa nel 2021 [10.1109/DAC18074.2021.9586154].

On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage

Cipolletta A.;Calimera A.
2021

Abstract

The memory space taken to host and process large tensor graphs is a limiting factor for embedded ConvNets. Even though many data-driven compression pipelines have proven their efficacy, this work shows there is still room for optimization at the intersection with compute-oriented optimizations. We demonstrate that tensor pruning via weight sparsification can cooperate with a model-agnostic tiling strategy, leading ConvNets towards a new feasible region of the solution space. The collected results show for the first time fast versions of MobileNets deployed at full scale on an ARM M7 core with 512KB of RAM and 2MB of FLASH memory.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2961251