Increase in chip power density results in higher operating temperatures, and thermal gradients (spatial and temporal) arise due to areas of the die with different power consumption. Thermal variations affect normal operation of nanoelectronic circuits in various dimensions, including reliability, leakage power and delay. And the picture will get more complicated (possibly worse) for CMOS devices with feature size below 45 nm. This paper provides an overview of some of the most recent design and synthesis techniques that will help in reducing the run-time temperature, as well as governing the effects of on-chip thermal gradients in the future generations of CMOS integrated circuits.
|Titolo:||Thermal-Aware Design Techniques for Nanometer CMOS Circuits|
|Data di pubblicazione:||2008|
|Digital Object Identifier (DOI):||10.1166/jolpe.2008.190|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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