VISWESWARA SATHANUR, ASHOKA

VISWESWARA SATHANUR, ASHOKA  

Dipartimento di Automatica Informatica (attivo dal 01/01/1900 al 31/12/2011)  

A. SATHANUR; SATHANUR A  

016491  

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Risultati 1 - 12 di 12 (tempo di esecuzione: 0.023 secondi).
Citazione Data di pubblicazione Autori File
A Scalable Algorithmic Framework for Row-Based Power-Gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 379-384. ((Intervento presentato al convegno DATE '08. Design, Automation and Test in Europe tenutosi a Munich (DEU) nel 10-14 March 2008 [10.1109/DATE.2008.4484710]. 1-gen-2008 VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology / Calimera, Andrea; Macii, Alberto; Pullini, A.; VISWESWARA SATHANUR, Ashoka; Benini, L.; Macii, Enrico; Poncino, Massimo. - (2007), pp. 501-504. ((Intervento presentato al convegno GLSVLSI-07: ACM/IEEE 17th Great Lakes Symposium on VLSI tenutosi a Stresa nel Marzo [10.1145/1228784.1228903]. 1-gen-2007 CALIMERA, ANDREAMACII, AlbertoVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + -
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers / Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 162-167. ((Intervento presentato al convegno ISLPED-06: ACM/IEEE International Symposium on Low Power Electronics and Design tenutosi a Tegernsee, Germany [10.1109/LPE.2006.4271829]. 1-gen-2006 DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Dynamic thermal clock skew compensation using tunable delay buffers / Chakraborty, A.; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P.; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 16:6(2008), pp. 639-649. [10.1109/TVLSI.2008.2000248] 1-gen-2008 DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + 1856364.pdf
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 1-6. ((Intervento presentato al convegno DATE-07: IEEE Design Automation and Test in Europe tenutosi a Nizza, Francia nel 16-20 April 2007 [10.1109/DATE.2007.364520]. 1-gen-2007 VISWESWARA SATHANUR, ASHOKACALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations / Macii, Alberto; Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Enrico; Poncino, Massimo. - In: INTEGRATION. - ISSN 0167-9260. - 41:1(2008), pp. 2-8. [10.1016/j.vlsi.2007.03.002] 1-gen-2008 MACII, AlbertoDURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + -
Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits / Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 33-36. ((Intervento presentato al convegno ISCAS-06: IEEE International Conference on Circuits and Systems tenutosi a Kos Island, Greece [10.1109/ISCAS.2006.1692515]. 1-gen-2006 DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Multiple power-gating domain (multi-VGND)architecture for improved leakage power reduction / VISWESWARA SATHANUR, Ashoka; Luca, Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 51-56. ((Intervento presentato al convegno ISLPED-08:International Symposium on Low Power Electronics and Design tenutosi a Bangalore, India [10.1145/1393921.1393938]. 1-gen-2008 VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; A., Pullini; L., Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008). ((Intervento presentato al convegno ISCAS 2008 tenutosi a Seattle, WA nel 18-21 May 2008 [10.1109/ISCAS.2008.4542029]. 1-gen-2008 VISWESWARA SATHANUR, ASHOKACALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Optimal sleep transistor synthesis under timing and area constraints / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 177-182. ((Intervento presentato al convegno GLSVLSI '08: 18th ACM Great Lakes symposium on VLSI tenutosi a Orlando, Florida nel May 04-06, 2008 [10.1145/1366110.1366155]. 1-gen-2008 VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Thermal-Aware Design Techniques for Nanometer CMOS Circuits / Calimera, Andrea; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Bahar, I; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - In: JOURNAL OF LOW POWER ELECTRONICS. - ISSN 1546-1998. - 3:(2008), pp. 374-384. [10.1166/jolpe.2008.190] 1-gen-2008 CALIMERA, ANDREADURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -
Timing-driven row-based power gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 104-109. ((Intervento presentato al convegno ISLPED-07: ACM/IEEE International Symposium on Low PowerElectronics and Design tenutosi a Portland, Oregon nel Agosto 2007 [10.1145/1283780.1283803]. 1-gen-2007 VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + -