Archivio Istituzionale della RicercaVISWESWARA SATHANUR, ASHOKA
VISWESWARA SATHANUR, ASHOKA
Dipartimento di Automatica Informatica (attivo dal 01/01/1900 al 31/12/2011)
A. SATHANUR; SATHANUR A
016491
A Scalable Algorithmic Framework for Row-Based Power-Gating
2008 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Multiple power-gating domain (multi-VGND)architecture for improved leakage power reduction
2008 VISWESWARA SATHANUR, Ashoka; Luca, Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits
2008 VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; A., Pullini; L., Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Optimal sleep transistor synthesis under timing and area constraints
2008 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
2007 Calimera, Andrea; Macii, Alberto; Pullini, A.; VISWESWARA SATHANUR, Ashoka; Benini, L.; Macii, Enrico; Poncino, Massimo
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing
2007 VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Timing-driven row-based power gating
2007 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers
2006 Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits
2006 Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Scalable Algorithmic Framework for Row-Based Power-Gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 379-384. (Intervento presentato al convegno DATE '08. Design, Automation and Test in Europe tenutosi a Munich (DEU) nel 10-14 March 2008) [10.1109/DATE.2008.4484710]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Multiple power-gating domain (multi-VGND)architecture for improved leakage power reduction / VISWESWARA SATHANUR, Ashoka; Luca, Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 51-56. (Intervento presentato al convegno ISLPED-08:International Symposium on Low Power Electronics and Design tenutosi a Bangalore, India) [10.1145/1393921.1393938]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; A., Pullini; L., Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008). (Intervento presentato al convegno ISCAS 2008 tenutosi a Seattle, WA nel 18-21 May 2008) [10.1109/ISCAS.2008.4542029]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKACALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Optimal sleep transistor synthesis under timing and area constraints / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 177-182. (Intervento presentato al convegno GLSVLSI '08: 18th ACM Great Lakes symposium on VLSI tenutosi a Orlando, Florida nel May 04-06, 2008) [10.1145/1366110.1366155]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology / Calimera, Andrea; Macii, Alberto; Pullini, A.; VISWESWARA SATHANUR, Ashoka; Benini, L.; Macii, Enrico; Poncino, Massimo. - (2007), pp. 501-504. (Intervento presentato al convegno GLSVLSI-07: ACM/IEEE 17th Great Lakes Symposium on VLSI tenutosi a Stresa nel Marzo) [10.1145/1228784.1228903]. | 1-gen-2007 | CALIMERA, ANDREAMACII, AlbertoVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + | - |
| Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 1-6. (Intervento presentato al convegno DATE-07: IEEE Design Automation and Test in Europe tenutosi a Nizza, Francia nel 16-20 April 2007) [10.1109/DATE.2007.364520]. | 1-gen-2007 | VISWESWARA SATHANUR, ASHOKACALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Timing-driven row-based power gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 104-109. (Intervento presentato al convegno ISLPED-07: ACM/IEEE International Symposium on Low PowerElectronics and Design tenutosi a Portland, Oregon nel Agosto 2007) [10.1145/1283780.1283803]. | 1-gen-2007 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers / Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 162-167. (Intervento presentato al convegno ISLPED-06: ACM/IEEE International Symposium on Low Power Electronics and Design tenutosi a Tegernsee, Germany) [10.1109/LPE.2006.4271829]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits / Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 33-36. (Intervento presentato al convegno ISCAS-06: IEEE International Conference on Circuits and Systems tenutosi a Kos Island, Greece) [10.1109/ISCAS.2006.1692515]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |