Archivio Istituzionale della RicercaDURAISAMI, KARTHIK
DURAISAMI, KARTHIK
Dipartimento di Automatica Informatica (attivo dal 01/01/1900 al 31/12/2011)
015094
Dynamic thermal clock skew compensation using tunable delay buffers
2008 Chakraborty, A.; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P.; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Energy Efficiency Bounds of Pulse-Encoded Buses
2008 Duraisami, Karthik; Poncino, Massimo; Macii, Enrico
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
2008 Macii, Alberto; Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Enrico; Poncino, Massimo
Thermal-Aware Design Techniques for Nanometer CMOS Circuits
2008 Calimera, Andrea; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Bahar, I; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew
2007 Duraisami, Karthik; Sithambaram, P; Sathanur, A; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective
2006 Ashutosh, Chakraborty; Duraisami, Karthik; VISWESWARA SATHANUR, A.; Prassanna, Sithambaram; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers
2006 Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits
2006 Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology
2006 Chakraborty, A; Sithambaram, P; Duraisami, Karthik; Poncino, Massimo; Macii, Alberto; Macii, Enrico
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Dynamic thermal clock skew compensation using tunable delay buffers / Chakraborty, A., Duraisami, K., VISWESWARA SATHANUR, A., Sithambaram, P., Macii, A., Macii, E., Poncino, M.. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 16:6(2008), pp. 639-649. [10.1109/TVLSI.2008.2000248] | 1-gen-2008 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Energy Efficiency Bounds of Pulse-Encoded Buses / Duraisami, K., Poncino, M., Macii, E.. - (2008), pp. 183-188. (GLS-VLSI-08: ACM/IEEE 18th Great Lakes Symposium on VLSI Orlando, FL ) [10.1145/1366110.1366156]. | 1-gen-2008 | DURAISAMI, KARTHIKPONCINO, MASSIMOMACII, Enrico | - |
| Implementation of a thermal management unit for canceling temperature-dependent clock skew variations / Macii, A., Chakraborty, A., Duraisami, K., VISWESWARA SATHANUR, A., Sithambaram, P., Macii, E., Poncino, M.. - In: INTEGRATION. - ISSN 0167-9260. - 41:1(2008), pp. 2-8. [10.1016/j.vlsi.2007.03.002] | 1-gen-2008 | MACII, AlbertoDURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + | - |
| Thermal-Aware Design Techniques for Nanometer CMOS Circuits / Calimera, A., Duraisami, K., VISWESWARA SATHANUR, A., Sithambaram, P., Bahar, I., Macii, A., Macii, E., Poncino, M.. - In: JOURNAL OF LOW POWER ELECTRONICS. - ISSN 1546-1998. - 3:(2008), pp. 374-384. [10.1166/jolpe.2008.190] | 1-gen-2008 | CALIMERA, ANDREADURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew / Duraisami, K., Sithambaram, P., Sathanur, A., Macii, A., Macii, E., Poncino, M.. - (2007), pp. 1061-1064. (ISCAS-07: IEEE International Conference on Circuits and Systems New Orleans, Louisiana 27-30 May 2007) [10.1109/ISCAS.2007.378192]. | 1-gen-2007 | DURAISAMI, KARTHIKMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective / Ashutosh, C., Duraisami, K., VISWESWARA SATHANUR, A., Prassanna, S., Macii, A., Macii, E., Poncino, M.. - (2006), pp. 214-224. (PATMOS-06: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation Montpellier, France ) [10.1007/11847083_21]. | 1-gen-2006 | DURAISAMI, KARTHIKMACII, AlbertoENRICO MACIIPONCINO, MASSIMO + | - |
| Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers / Chakraborty, A., Duraisami, K., Sithambaram, P., VISWESWARA SATHANUR, A., Macii, A., Macii, E., Poncino, M.. - (2006), pp. 162-167. (ISLPED-06: ACM/IEEE International Symposium on Low Power Electronics and Design Tegernsee, Germany ) [10.1109/LPE.2006.4271829]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits / Chakraborty, A., Duraisami, K., VISWESWARA SATHANUR, A., Sithambaram, P., Macii, A., Macii, E., Poncino, M.. - (2006), pp. 33-36. (ISCAS-06: IEEE International Conference on Circuits and Systems Kos Island, Greece ) [10.1109/ISCAS.2006.1692515]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology / Chakraborty, A., Sithambaram, P., Duraisami, K., Poncino, M., Macii, A., Macii, E.. - (2006), pp. 832-837. (DATE-06: IEEE Design Automation and Test in Europe Munich, Germany ) [10.1109/DATE.2006.243740]. | 1-gen-2006 | DURAISAMI, KARTHIKPONCINO, MASSIMOMACII, AlbertoMACII, Enrico + | - |