Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.

Optimal sleep transistor synthesis under timing and area constraints / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 177-182. (Intervento presentato al convegno GLSVLSI '08: 18th ACM Great Lakes symposium on VLSI tenutosi a Orlando, Florida nel May 04-06, 2008) [10.1145/1366110.1366155].

Optimal sleep transistor synthesis under timing and area constraints

VISWESWARA SATHANUR, ASHOKA;MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO
2008

Abstract

Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.
2008
9781595939999
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1830961
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