PORTO @ Archivio Istituzionale della Ricerca

PONCINO, MASSIMO
 Distribuzione geografica
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Continente #
EU - Europa 45.154
NA - Nord America 40.018
AS - Asia 6.235
AF - Africa 524
SA - Sud America 131
Continente sconosciuto - Info sul continente non disponibili 39
OC - Oceania 22
Totale 92.123
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Nazione #
US - Stati Uniti d'America 39.742
FR - Francia 9.294
GB - Regno Unito 9.288
IT - Italia 9.059
DE - Germania 8.796
CN - Cina 3.390
UA - Ucraina 2.577
NL - Olanda 1.424
TR - Turchia 1.030
IE - Irlanda 1.009
RU - Federazione Russa 815
CH - Svizzera 711
SE - Svezia 641
SG - Singapore 630
FI - Finlandia 422
SN - Senegal 344
KR - Corea 272
CA - Canada 264
IN - India 252
BE - Belgio 219
AT - Austria 200
JP - Giappone 179
JO - Giordania 124
ES - Italia 115
HK - Hong Kong 115
GH - Ghana 103
EU - Europa 84
RO - Romania 70
BG - Bulgaria 68
BR - Brasile 66
TW - Taiwan 61
CZ - Repubblica Ceca 51
IR - Iran 45
AP - ???statistics.table.value.countryCode.AP??? 41
IL - Israele 41
MY - Malesia 40
VN - Vietnam 36
EE - Estonia 35
DK - Danimarca 28
CO - Colombia 27
AE - Emirati Arabi Uniti 26
CL - Cile 26
PL - Polonia 24
PT - Portogallo 23
AU - Australia 22
PK - Pakistan 17
HR - Croazia 14
NG - Nigeria 14
TH - Thailandia 14
GR - Grecia 12
BY - Bielorussia 11
ZA - Sudafrica 11
CI - Costa d'Avorio 10
LU - Lussemburgo 10
SA - Arabia Saudita 10
TN - Tunisia 10
EG - Egitto 9
ID - Indonesia 9
KZ - Kazakistan 9
NO - Norvegia 9
PH - Filippine 9
SK - Slovacchia (Repubblica Slovacca) 9
MX - Messico 8
PE - Perù 8
IQ - Iraq 7
UZ - Uzbekistan 6
DZ - Algeria 5
LV - Lettonia 4
SC - Seychelles 4
SD - Sudan 4
SO - Somalia 4
BD - Bangladesh 3
HU - Ungheria 3
LI - Liechtenstein 3
LK - Sri Lanka 3
QA - Qatar 3
AL - Albania 2
AR - Argentina 2
EC - Ecuador 2
GE - Georgia 2
KE - Kenya 2
KH - Cambogia 2
KW - Kuwait 2
LT - Lituania 2
MU - Mauritius 2
NP - Nepal 2
RS - Serbia 2
SI - Slovenia 2
A1 - Anonimo 1
A2 - ???statistics.table.value.countryCode.A2??? 1
AM - Armenia 1
AZ - Azerbaigian 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
DO - Repubblica Dominicana 1
GT - Guatemala 1
IS - Islanda 1
KG - Kirghizistan 1
LA - Repubblica Popolare Democratica del Laos 1
LB - Libano 1
Totale 92.117
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Città #
Ashburn 10.523
Southend 8.670
Seattle 5.324
Fairfield 3.426
Chandler 1.910
Turin 1.824
Woodbridge 1.739
Boardman 1.469
Houston 1.432
Princeton 1.393
Zhengzhou 1.381
Jacksonville 1.277
Cambridge 1.254
Wilmington 1.192
Ann Arbor 1.134
Torino 1.105
Dublin 973
Izmir 831
Berlin 826
San Ramon 816
Frankfurt 686
Herkenbosch 654
Bern 648
Milan 605
Beijing 527
Chicago 518
Hangzhou 429
San Donato Milanese 419
Helsinki 395
Shanghai 358
Zaporozhye 351
Singapore 344
Pennsylvania Furnace 311
Baltimore 310
Saint Petersburg 289
Des Moines 268
Overberg 268
Monopoli 242
Council Bluffs 222
Bologna 221
Mountain View 215
Bremen 197
Vienna 193
Padua 188
Brussels 172
San Diego 158
Amsterdam 150
Rome 139
Fremont 134
Redwood City 134
Guangzhou 130
Malatya 119
Rotterdam 113
Lecce 104
San Francisco 103
Falls Church 93
Buffalo 87
Toronto 85
Norwalk 84
Dearborn 83
Moscow 81
Putian 75
Melun 73
Wenzhou 69
Ottawa 68
Milano 65
Andover 64
Montréal 64
Modena 63
Redmond 63
Sofia 62
San Jose 56
Verona 56
Shenzhen 54
Munich 51
Seoul 48
London 47
Treviso 45
Osaka 42
Paris 41
Washington 41
Mcallen 40
Kiev 39
Kocaeli 39
Overland Park 38
New York 37
Columbus 34
Frankfurt am Main 34
Galati 34
Nanjing 34
San Antonio 32
Atlanta 31
Ningbo 31
Brno 29
Podenzano 29
Central District 27
Las Vegas 27
Madrid 27
Kansas City 26
Bari 25
Totale 61.086
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Nome #
Using Connectivity and Spectral Methods to Characterize the Structure of Sequential Logic Circuits 1.232
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 634
Data-Driven Clock Gating for Digital Filters 618
On-chip Thermal Modeling Based on SPICE Simulation 603
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 541
An on-chip all-digital PV-monitoring architecture for digital IPs 522
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 507
Modeling of thermally induced skew variations in clock distribution network 489
Fondamenti di Informatica: 100 Esercizi d'Esame Svolti 473
PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI 473
Modeling of the Charging Behavior of Li-Ion Batteries based on Manufacturer’s Data 461
RTL Estimation of Steering Logic Power 455
GIS-Based Optimal Photovoltaic Panel Floorplanning for Residential Installations 441
Aging Effects of Leakage Optimizations for Caches 427
A Low-Power Encoding Scheme for GigaByte Video Interfaces 425
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 424
A Compact Macromodel for the Charge Phase of a Battery with Typical Charging Protocol 424
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding 422
Power Models for Semi-Autonomous RTL Macros 411
A Statistic Power Model for Non-synthetic RTL Operators 389
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 386
A Top-down Constraint-driven Methodology for Smart System Design 384
A Framework for Efficient Evaluation and Comparison of EES Models 382
Energy-efficient digital processing via Approximate Computing 380
Buffering of frequent accesses for reduced cache aging 364
An Efficient Simulation Methodology for Electrical Energy Systems 364
Partitioned cache architectures for reduced NBTI-induced aging 363
Application of symbolic FSM Markovian analysis to protocol verification 361
Approximate energy-efficient encoding for serial interfaces 355
The Human Brain Project and Neuromorphic computing 352
Power-Gating: More Than Leakage Savings 348
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 346
A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors 343
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Sub-Banking 340
Towards Multi-Domain and Multi-Physical Electronic Design 339
Zero-Transition Serial Encoding for Image Sensors 328
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 323
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting 323
An Open-Source Framework for Formal Specification and Simulation of Electrical Energy Systems 322
An integrated thermal estimation framework for industrial embedded platforms. 320
Fast thermal simulation using SystemC-AMS 320
An integrated thermal estimation framework for industrial embedded platforms 319
A refinement methodology for clock gating optimization at layout level in digital circuits 317
A Li-ion battery charge protocol with optimal aging-quality of service trade-off 317
A Framework with Temperature-Aware Accuracy Levels for Battery Modeling from Datasheets 316
Design Techniques and Architectures for Low-Leakage SRAMs 314
Property verification of communication protocols based on probabilistic reachability analysis 312
An Automated Framework for Generating Variable-Accuracy Battery Models from Datasheet Information 310
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits 307
Empirical derivation of upper and lower bounds of NBTI aging for embedded cores 307
An equation-based battery cycle life model for various battery chemistries 305
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 305
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns 303
Characterizing the activity factor in NBTI aging models for embedded cores 300
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities 300
Delay model for reconfigurable logic gates based on graphene PN-junctions 299
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 299
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 298
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 295
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 295
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 292
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 291
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 290
Aging and cost optimal residential charging for plug-in EVs 290
Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization 289
VHDL Simulation: A Flexible Approach to Verification and Performance Analysis of Communication Protocols 288
Dual-Vt Assignment Policies in ITD-Aware Synthesis 287
Efficient analysis of communication protocols using VHDL modeling and simulation 287
Exploration of different implementation styles for graphene-based reconfigurable gates 287
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 285
Automated generation of battery aging models from datasheets 285
A Fully Standard-Cell Delay Measurement Circuit for Timing Variability Detection 285
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 285
Hardware simulation: a flexible approach to verification and performance evaluation of communication protocols 283
Dynamic thermal clock skew compensation using tunable delay buffers 282
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 281
Modeling and Simulation of the Power Flow in Smart Systems 280
A unified model of power sources for the simulation of electrical energy systems 278
Fast Computation of Discharge Current Upper Bounds for Clustered Power-Gating 278
A Statistical Model of Cell-to-Cell Variation Li-ion Batteries for System-Level Design 277
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation 277
A methodology for the design of dynamic accuracy operators by runtime back bias 276
A Scalable Algorithmic Framework for Row-Based Power-Gating 274
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective 274
System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications 273
Addressing the Smart Systems Design Challenge: The SMAC Platform 273
Automatic Selection of Instruction Op-Codes of Low-Power Core Processors 271
Thermal-aware floorplanning exploration for 3D multi-core architectures. 271
Discharge Current Steering for Battery Lifetime Optimization 270
A cosimulation methodology for HW/SW validation and performance estimation 270
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support 268
Energy-optimal caches with guaranteed lifetime 268
Aging-Aware Caches with Graceful Degradation of Performance 267
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 267
Computer-Aided Design of Electrical Energy Systems 266
A Discrete-Time Battery Model for High-Level Power Estimation 266
Glitch power minimization by selective gate freezing 265
Timing-driven row-based power gating 265
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation 265
Reducing Peak Power Consumption of Combinational Test Sets 265
Totale 34.623
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Categoria #
all - tutte 228.135
article - articoli 67.117
book - libri 2.613
conference - conferenze 151.556
curatela - curatele 0
other - altro 0
patent - brevetti 385
selected - selezionate 0
volume - volumi 6.464
Totale 456.270
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202010.947 939 771 286 1.519 1.273 1.167 901 1.525 1.275 683 348 260
2020/20217.381 919 1.083 287 962 324 655 307 600 384 1.054 454 352
2021/20225.002 400 376 296 152 176 384 237 209 170 449 832 1.321
2022/20237.682 743 1.239 251 652 804 964 744 378 681 107 294 825
2023/20242.557 177 226 236 125 241 276 150 174 61 127 268 496
2024/2025114 114 0 0 0 0 0 0 0 0 0 0 0
Totale 92.878