PORTO @ Archivio Istituzionale della Ricerca

PONCINO, MASSIMO
 Distribuzione geografica
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Continente #
EU - Europa 51.940
NA - Nord America 50.560
AS - Asia 28.266
SA - Sud America 2.035
AF - Africa 762
Continente sconosciuto - Info sul continente non disponibili 47
OC - Oceania 33
Totale 133.643
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Nazione #
US - Stati Uniti d'America 50.053
IT - Italia 10.167
FR - Francia 9.844
GB - Regno Unito 9.429
DE - Germania 9.278
SG - Singapore 8.480
CN - Cina 7.455
VN - Vietnam 5.838
RU - Federazione Russa 4.302
UA - Ucraina 2.624
BR - Brasile 1.702
NL - Olanda 1.585
TR - Turchia 1.403
KR - Corea 1.220
HK - Hong Kong 1.187
IE - Irlanda 1.037
IN - India 807
CH - Svizzera 735
SE - Svezia 666
FI - Finlandia 554
AT - Austria 502
CA - Canada 371
SN - Senegal 358
JP - Giappone 317
BE - Belgio 269
TW - Taiwan 183
TH - Thailandia 173
PH - Filippine 172
ID - Indonesia 165
ES - Italia 162
JO - Giordania 150
IQ - Iraq 145
BD - Bangladesh 118
GH - Ghana 103
AR - Argentina 96
PK - Pakistan 93
IL - Israele 87
EU - Europa 84
MX - Messico 82
RO - Romania 82
PL - Polonia 80
BG - Bulgaria 74
ZA - Sudafrica 69
CL - Cile 64
CZ - Repubblica Ceca 60
MY - Malesia 58
IR - Iran 56
EC - Ecuador 49
CO - Colombia 46
AE - Emirati Arabi Uniti 41
AP - ???statistics.table.value.countryCode.AP??? 41
PT - Portogallo 40
EE - Estonia 36
UZ - Uzbekistan 36
DK - Danimarca 35
MA - Marocco 34
TN - Tunisia 32
AU - Australia 31
EG - Egitto 31
SA - Arabia Saudita 31
VE - Venezuela 30
KE - Kenya 29
KZ - Kazakistan 23
LT - Lituania 23
NG - Nigeria 23
GR - Grecia 21
DZ - Algeria 20
HR - Croazia 20
AZ - Azerbaigian 19
PE - Perù 18
PY - Paraguay 17
BY - Bielorussia 16
AL - Albania 15
CI - Costa d'Avorio 14
NO - Norvegia 14
SK - Slovacchia (Repubblica Slovacca) 13
LB - Libano 12
OM - Oman 12
LU - Lussemburgo 11
NP - Nepal 11
HU - Ungheria 10
LK - Sri Lanka 10
UY - Uruguay 10
CR - Costa Rica 9
BH - Bahrain 8
LV - Lettonia 8
MU - Mauritius 8
PS - Palestinian Territory 8
QA - Qatar 8
SY - Repubblica araba siriana 8
JM - Giamaica 7
RS - Serbia 7
XK - ???statistics.table.value.countryCode.XK??? 7
ET - Etiopia 6
GE - Georgia 6
KG - Kirghizistan 6
KW - Kuwait 6
SI - Slovenia 6
AM - Armenia 5
BB - Barbados 5
Totale 133.531
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Città #
Ashburn 11.622
Southend 8.670
Seattle 5.329
Singapore 4.805
Fairfield 3.426
Turin 2.482
San Jose 2.114
Boardman 1.916
Chandler 1.911
Woodbridge 1.739
Ho Chi Minh City 1.520
Houston 1.449
Zhengzhou 1.400
Princeton 1.393
Hanoi 1.363
Jacksonville 1.278
Cambridge 1.254
Wilmington 1.192
Ann Arbor 1.134
Beijing 1.114
Torino 1.105
Dublin 999
Santa Clara 974
Hong Kong 922
Izmir 833
Berlin 827
San Ramon 816
Milan 697
Council Bluffs 690
Dallas 687
Frankfurt 686
Herkenbosch 654
Bern 648
Moscow 619
Hefei 594
Chicago 538
Los Angeles 487
Seoul 464
Helsinki 449
Tongling 444
Hangzhou 434
Lauterbourg 423
San Donato Milanese 419
Shanghai 403
Zaporozhye 351
Istanbul 333
Baltimore 311
Pennsylvania Furnace 311
Vienna 310
Des Moines 291
Saint Petersburg 289
Da Nang 277
Overberg 268
Nuremberg 262
Monopoli 242
Buffalo 236
Bologna 229
Brussels 219
Haiphong 219
Mountain View 215
Bremen 197
Padua 188
Amsterdam 179
Guangzhou 167
New York 163
Rome 163
San Diego 159
Munich 154
São Paulo 147
Fremont 134
Redwood City 134
San Francisco 131
Frankfurt am Main 128
The Dalles 127
Jakarta 121
Malatya 119
Groningen 115
Rotterdam 113
Toronto 106
Lecce 104
Falls Church 93
Columbus 91
North Bergen 89
London 88
Tokyo 86
Dearborn 85
Norwalk 85
Ottawa 79
Putian 75
Hải Dương 74
Melun 73
Bangkok 70
Wenzhou 70
Shenzhen 67
Milano 65
Andover 64
Montréal 64
Modena 63
Redmond 63
Sofia 63
Totale 81.642
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Nome #
Using Connectivity and Spectral Methods to Characterize the Structure of Sequential Logic Circuits 1.301
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 742
On-chip Thermal Modeling Based on SPICE Simulation 719
Data-Driven Clock Gating for Digital Filters 717
Memory Design Techniques for Low-Energy Embedded Systems 704
Modeling of thermally induced skew variations in clock distribution network 677
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 643
An on-chip all-digital PV-monitoring architecture for digital IPs 633
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 611
Aging Effects of Leakage Optimizations for Caches 581
PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI 568
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 566
Modeling of the Charging Behavior of Li-Ion Batteries based on Manufacturer’s Data 563
GIS-Based Optimal Photovoltaic Panel Floorplanning for Residential Installations 562
Fondamenti di Informatica: 100 Esercizi d'Esame Svolti 558
RTL Estimation of Steering Logic Power 531
A Compact Macromodel for the Charge Phase of a Battery with Typical Charging Protocol 527
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding 524
Buffering of frequent accesses for reduced cache aging 510
Approximate energy-efficient encoding for serial interfaces 498
A Low-Power Encoding Scheme for GigaByte Video Interfaces 498
Power Models for Semi-Autonomous RTL Macros 496
A Top-down Constraint-driven Methodology for Smart System Design 495
Partitioned cache architectures for reduced NBTI-induced aging 481
A Statistic Power Model for Non-synthetic RTL Operators 472
Power-Gating: More Than Leakage Savings 471
Energy-efficient digital processing via Approximate Computing 469
Fast thermal simulation using SystemC-AMS 467
A Framework for Efficient Evaluation and Comparison of EES Models 467
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities 464
Zero-Transition Serial Encoding for Image Sensors 463
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 460
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 457
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Sub-Banking 448
An Efficient Simulation Methodology for Electrical Energy Systems 444
A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors 441
Towards Multi-Domain and Multi-Physical Electronic Design 440
The Human Brain Project and Neuromorphic computing 434
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 430
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting 425
A Li-ion battery charge protocol with optimal aging-quality of service trade-off 424
An Open-Source Framework for Formal Specification and Simulation of Electrical Energy Systems 423
Application of symbolic FSM Markovian analysis to protocol verification 421
A Framework with Temperature-Aware Accuracy Levels for Battery Modeling from Datasheets 417
An equation-based battery cycle life model for various battery chemistries 417
An Automated Framework for Generating Variable-Accuracy Battery Models from Datasheet Information 413
Empirical derivation of upper and lower bounds of NBTI aging for embedded cores 413
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 412
Modeling and Simulation of the Power Flow in Smart Systems 409
A Discrete-Time Battery Model for High-Level Power Estimation 408
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 407
Automated generation of battery aging models from datasheets 406
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns 405
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 403
An integrated thermal estimation framework for industrial embedded platforms 403
Design Techniques and Architectures for Low-Leakage SRAMs 401
Dynamic thermal clock skew compensation using tunable delay buffers 400
An integrated thermal estimation framework for industrial embedded platforms. 398
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 393
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 391
A methodology for the design of dynamic accuracy operators by runtime back bias 391
Property verification of communication protocols based on probabilistic reachability analysis 389
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits 388
Delay model for reconfigurable logic gates based on graphene PN-junctions 387
A cosimulation methodology for HW/SW validation and performance estimation 386
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 385
A refinement methodology for clock gating optimization at layout level in digital circuits 384
A Statistical Model of Cell-to-Cell Variation Li-ion Batteries for System-Level Design 383
Addressing the Smart Systems Design Challenge: The SMAC Platform 383
Aging and cost optimal residential charging for plug-in EVs 382
A Smart Meter Infrastructure for Smart Grid IoT Applications 380
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 379
VHDL Simulation: A Flexible Approach to Verification and Performance Analysis of Communication Protocols 379
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective 379
Characterizing the activity factor in NBTI aging models for embedded cores 378
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 378
A Fully Standard-Cell Delay Measurement Circuit for Timing Variability Detection 378
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 376
Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology 375
A Scalable Algorithmic Framework for Row-Based Power-Gating 374
A temperature-aware battery cycle life model for different battery chemistries 374
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 372
A unified model of power sources for the simulation of electrical energy systems 372
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 372
Discrete-time battery models for system-level low-power design 371
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation 369
Energy-optimal caches with guaranteed lifetime 369
Exploration of different implementation styles for graphene-based reconfigurable gates 364
Dual-Vt Assignment Policies in ITD-Aware Synthesis 362
NBTI effects on tree-like clock distribution networks 362
Fast Computation of Discharge Current Upper Bounds for Clustered Power-Gating 362
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 361
Efficient analysis of communication protocols using VHDL modeling and simulation 361
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 359
Selective Instruction Compression for Memory Energy Reduction in Embedded Systems 358
Modeling of Physical Defects in PN-Junction Based Graphene Devices 358
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 357
Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization 356
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support 353
Computer-Aided Design of Electrical Energy Systems 352
Totale 45.019
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Categoria #
all - tutte 340.490
article - articoli 100.981
book - libri 4.640
conference - conferenze 223.986
curatela - curatele 0
other - altro 0
patent - brevetti 617
selected - selezionate 0
volume - volumi 10.266
Totale 680.980
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021806 0 0 0 0 0 0 0 0 0 0 454 352
2021/20225.002 400 376 296 152 176 384 237 209 170 449 832 1.321
2022/20237.682 743 1.239 251 652 804 964 744 378 681 107 294 825
2023/20242.557 177 226 236 125 241 276 150 174 61 127 268 496
2024/202513.354 184 1.359 738 1.703 733 543 854 1.304 2.035 785 805 2.311
2025/202628.360 1.724 1.168 1.792 2.456 1.560 1.562 4.034 2.566 6.835 4.121 542 0
Totale 134.478