PORTO @ Archivio Istituzionale della Ricerca

PONCINO, MASSIMO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
EU - Europa 47.148
NA - Nord America 45.559
AS - Asia 15.050
SA - Sud America 1.467
AF - Africa 623
Continente sconosciuto - Info sul continente non disponibili 42
OC - Oceania 24
Totale 109.913
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 45.170
IT - Italia 9.480
FR - Francia 9.393
GB - Regno Unito 9.353
DE - Germania 9.195
CN - Cina 6.350
SG - Singapore 4.690
UA - Ucraina 2.602
NL - Olanda 1.460
TR - Turchia 1.382
BR - Brasile 1.288
RU - Federazione Russa 1.228
IE - Irlanda 1.027
KR - Corea 889
CH - Svizzera 724
SE - Svezia 654
AT - Austria 488
FI - Finlandia 481
HK - Hong Kong 381
SN - Senegal 349
CA - Canada 320
IN - India 312
BE - Belgio 267
JP - Giappone 192
VN - Vietnam 148
ES - Italia 135
JO - Giordania 132
ID - Indonesia 125
GH - Ghana 103
EU - Europa 84
IL - Israele 79
BG - Bulgaria 73
RO - Romania 71
TW - Taiwan 70
IR - Iran 55
CZ - Repubblica Ceca 53
PL - Polonia 51
BD - Bangladesh 50
IQ - Iraq 49
MX - Messico 42
MY - Malesia 42
AP - ???statistics.table.value.countryCode.AP??? 41
PK - Pakistan 38
CO - Colombia 36
AR - Argentina 35
CL - Cile 35
EE - Estonia 35
AE - Emirati Arabi Uniti 34
ZA - Sudafrica 32
EC - Ecuador 30
DK - Danimarca 29
PT - Portogallo 25
AU - Australia 23
MA - Marocco 20
SA - Arabia Saudita 20
TN - Tunisia 20
NG - Nigeria 17
UZ - Uzbekistan 17
EG - Egitto 16
GR - Grecia 16
KZ - Kazakistan 16
KE - Kenya 15
LT - Lituania 15
TH - Thailandia 15
HR - Croazia 14
PE - Perù 14
CI - Costa d'Avorio 13
VE - Venezuela 13
NO - Norvegia 12
BY - Bielorussia 11
DZ - Algeria 11
LU - Lussemburgo 11
SK - Slovacchia (Repubblica Slovacca) 11
PH - Filippine 9
PY - Paraguay 9
AL - Albania 7
LK - Sri Lanka 7
AZ - Azerbaigian 6
LV - Lettonia 6
NP - Nepal 6
UY - Uruguay 6
AM - Armenia 5
GE - Georgia 5
HU - Ungheria 5
BB - Barbados 4
DO - Repubblica Dominicana 4
GA - Gabon 4
JM - Giamaica 4
KG - Kirghizistan 4
KW - Kuwait 4
LB - Libano 4
OM - Oman 4
PS - Palestinian Territory 4
RS - Serbia 4
SC - Seychelles 4
SD - Sudan 4
SO - Somalia 4
TT - Trinidad e Tobago 4
BA - Bosnia-Erzegovina 3
CR - Costa Rica 3
Totale 109.860
Salva come PNG Salva come JPEG
Città #
Ashburn 10.858
Southend 8.670
Seattle 5.326
Fairfield 3.426
Singapore 2.459
Turin 2.014
Boardman 1.912
Chandler 1.911
Woodbridge 1.739
Houston 1.436
Zhengzhou 1.395
Princeton 1.393
Jacksonville 1.278
Cambridge 1.254
Wilmington 1.192
Ann Arbor 1.134
Torino 1.105
Beijing 1.001
Dublin 990
Santa Clara 931
Izmir 833
Berlin 826
San Ramon 816
Frankfurt 686
Milan 658
Herkenbosch 654
Bern 648
Council Bluffs 585
Dallas 575
Chicago 532
Tongling 444
Hangzhou 431
San Donato Milanese 419
Helsinki 406
Shanghai 392
Zaporozhye 351
Istanbul 325
Pennsylvania Furnace 311
Baltimore 310
Vienna 301
Saint Petersburg 289
Des Moines 270
Overberg 268
Hong Kong 260
Nuremberg 253
Seoul 249
Monopoli 242
Bologna 223
Brussels 218
Mountain View 215
Bremen 197
Buffalo 192
Padua 188
Hefei 186
Amsterdam 167
Los Angeles 165
Guangzhou 162
San Diego 158
Munich 152
Rome 151
Fremont 134
Redwood City 134
Malatya 119
San Francisco 117
Jakarta 115
Rotterdam 113
Lecce 104
São Paulo 101
Toronto 96
Falls Church 93
Moscow 86
Dearborn 84
Norwalk 84
Ottawa 79
Columbus 78
New York 78
Putian 75
Melun 73
Frankfurt am Main 72
Wenzhou 70
London 68
Milano 65
Andover 64
Montréal 64
Modena 63
Redmond 63
Sofia 63
Yubileyny 63
Shenzhen 60
San Jose 59
Verona 57
Hanoi 49
Paris 48
The Dalles 48
Treviso 47
Washington 44
Osaka 42
Porto Alegre 41
Atlanta 40
Belo Horizonte 40
Totale 69.125
Salva come PNG Salva come JPEG
Nome #
Using Connectivity and Spectral Methods to Characterize the Structure of Sequential Logic Circuits 1.266
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 675
Data-Driven Clock Gating for Digital Filters 668
On-chip Thermal Modeling Based on SPICE Simulation 650
Memory Design Techniques for Low-Energy Embedded Systems 589
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 581
An on-chip all-digital PV-monitoring architecture for digital IPs 566
Modeling of thermally induced skew variations in clock distribution network 563
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 547
Fondamenti di Informatica: 100 Esercizi d'Esame Svolti 518
PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI 513
Modeling of the Charging Behavior of Li-Ion Batteries based on Manufacturer’s Data 504
RTL Estimation of Steering Logic Power 492
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 480
GIS-Based Optimal Photovoltaic Panel Floorplanning for Residential Installations 480
Aging Effects of Leakage Optimizations for Caches 478
A Compact Macromodel for the Charge Phase of a Battery with Typical Charging Protocol 467
A Low-Power Encoding Scheme for GigaByte Video Interfaces 461
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding 455
Power Models for Semi-Autonomous RTL Macros 449
A Top-down Constraint-driven Methodology for Smart System Design 432
A Statistic Power Model for Non-synthetic RTL Operators 426
Buffering of frequent accesses for reduced cache aging 422
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 421
A Framework for Efficient Evaluation and Comparison of EES Models 416
Energy-efficient digital processing via Approximate Computing 413
Partitioned cache architectures for reduced NBTI-induced aging 411
Approximate energy-efficient encoding for serial interfaces 406
Power-Gating: More Than Leakage Savings 398
Application of symbolic FSM Markovian analysis to protocol verification 396
An Efficient Simulation Methodology for Electrical Energy Systems 396
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Sub-Banking 386
Towards Multi-Domain and Multi-Physical Electronic Design 384
The Human Brain Project and Neuromorphic computing 382
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 382
A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors 382
Zero-Transition Serial Encoding for Image Sensors 371
An Open-Source Framework for Formal Specification and Simulation of Electrical Energy Systems 362
A Li-ion battery charge protocol with optimal aging-quality of service trade-off 361
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting 359
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 356
Empirical derivation of upper and lower bounds of NBTI aging for embedded cores 356
A Framework with Temperature-Aware Accuracy Levels for Battery Modeling from Datasheets 354
An equation-based battery cycle life model for various battery chemistries 354
Property verification of communication protocols based on probabilistic reachability analysis 353
Fast thermal simulation using SystemC-AMS 353
A refinement methodology for clock gating optimization at layout level in digital circuits 350
An integrated thermal estimation framework for industrial embedded platforms. 350
An integrated thermal estimation framework for industrial embedded platforms 349
Design Techniques and Architectures for Low-Leakage SRAMs 348
An Automated Framework for Generating Variable-Accuracy Battery Models from Datasheet Information 347
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits 347
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 346
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 345
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 345
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns 343
Delay model for reconfigurable logic gates based on graphene PN-junctions 338
Characterizing the activity factor in NBTI aging models for embedded cores 338
VHDL Simulation: A Flexible Approach to Verification and Performance Analysis of Communication Protocols 336
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 336
Dynamic thermal clock skew compensation using tunable delay buffers 335
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities 334
Aging and cost optimal residential charging for plug-in EVs 333
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 331
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 329
Efficient analysis of communication protocols using VHDL modeling and simulation 329
A Discrete-Time Battery Model for High-Level Power Estimation 329
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 328
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 327
A Fully Standard-Cell Delay Measurement Circuit for Timing Variability Detection 327
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 326
Modeling and Simulation of the Power Flow in Smart Systems 325
Automated generation of battery aging models from datasheets 324
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 323
A unified model of power sources for the simulation of electrical energy systems 322
Exploration of different implementation styles for graphene-based reconfigurable gates 322
Hardware simulation: a flexible approach to verification and performance evaluation of communication protocols 321
A methodology for the design of dynamic accuracy operators by runtime back bias 321
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective 320
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 319
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 319
Dual-Vt Assignment Policies in ITD-Aware Synthesis 315
Addressing the Smart Systems Design Challenge: The SMAC Platform 315
Glitch power minimization by selective gate freezing 313
Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization 312
A Statistical Model of Cell-to-Cell Variation Li-ion Batteries for System-Level Design 312
A cosimulation methodology for HW/SW validation and performance estimation 312
A Scalable Algorithmic Framework for Row-Based Power-Gating 312
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation 310
Discrete-time battery models for system-level low-power design 309
Discharge Current Steering for Battery Lifetime Optimization 309
Selective Instruction Compression for Memory Energy Reduction in Embedded Systems 309
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 309
NBTI effects on tree-like clock distribution networks 307
Fast Computation of Discharge Current Upper Bounds for Clustered Power-Gating 307
A temperature-aware battery cycle life model for different battery chemistries 303
Computer-Aided Design of Electrical Energy Systems 302
Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces 301
Thermal-aware floorplanning exploration for 3D multi-core architectures. 301
Timing-driven row-based power gating 300
Totale 38.954
Salva come PNG Salva come JPEG
Categoria #
all - tutte 295.523
article - articoli 87.844
book - libri 4.135
conference - conferenze 194.358
curatela - curatele 0
other - altro 0
patent - brevetti 521
selected - selezionate 0
volume - volumi 8.665
Totale 591.046
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20215.379 0 0 287 962 324 655 307 600 384 1.054 454 352
2021/20225.002 400 376 296 152 176 384 237 209 170 449 832 1.321
2022/20237.682 743 1.239 251 652 804 964 744 378 681 107 294 825
2023/20242.557 177 226 236 125 241 276 150 174 61 127 268 496
2024/202513.361 184 1.359 738 1.703 733 543 854 1.304 2.035 785 809 2.314
2025/20264.610 1.740 1.174 1.696 0 0 0 0 0 0 0 0 0
Totale 110.735