PORTO @ Archivio Istituzionale della Ricerca

PONCINO, MASSIMO
 Distribuzione geografica
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Continente #
NA - Nord America 57.874
EU - Europa 53.940
AS - Asia 28.961
SA - Sud America 2.201
Continente sconosciuto - Info sul continente non disponibili 937
AF - Africa 786
OC - Oceania 39
Totale 144.738
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Nazione #
US - Stati Uniti d'America 56.356
IT - Italia 11.811
FR - Francia 9.877
GB - Regno Unito 9.510
DE - Germania 9.310
SG - Singapore 8.685
CN - Cina 7.511
VN - Vietnam 5.849
RU - Federazione Russa 4.327
UA - Ucraina 2.633
BR - Brasile 1.784
NL - Olanda 1.594
TR - Turchia 1.405
KR - Corea 1.233
HK - Hong Kong 1.201
IE - Irlanda 1.041
CA - Canada 951
IN - India 852
CH - Svizzera 740
SE - Svezia 739
FI - Finlandia 554
AT - Austria 506
BD - Bangladesh 368
SN - Senegal 358
JP - Giappone 335
BE - Belgio 270
PH - Filippine 186
TW - Taiwan 185
ES - Italia 184
TH - Thailandia 180
ID - Indonesia 178
JO - Giordania 150
IQ - Iraq 146
AR - Argentina 114
IL - Israele 111
GH - Ghana 106
MX - Messico 99
PK - Pakistan 99
RO - Romania 92
PL - Polonia 90
EU - Europa 84
BG - Bulgaria 75
CL - Cile 74
CR - Costa Rica 74
ZA - Sudafrica 70
EC - Ecuador 69
JM - Giamaica 68
CO - Colombia 64
MY - Malesia 63
CZ - Repubblica Ceca 60
IR - Iran 56
HN - Honduras 48
SV - El Salvador 47
EE - Estonia 45
DK - Danimarca 44
NI - Nicaragua 44
PR - Porto Rico 44
VE - Venezuela 44
AE - Emirati Arabi Uniti 42
PT - Portogallo 42
AP - ???statistics.table.value.countryCode.AP??? 41
MA - Marocco 38
AU - Australia 37
TT - Trinidad e Tobago 37
GT - Guatemala 36
TN - Tunisia 36
UZ - Uzbekistan 36
SA - Arabia Saudita 35
EG - Egitto 31
CW - ???statistics.table.value.countryCode.CW??? 29
KE - Kenya 29
KZ - Kazakistan 24
LT - Lituania 24
AL - Albania 23
GR - Grecia 23
NG - Nigeria 23
DZ - Algeria 20
HR - Croazia 20
PE - Perù 20
AZ - Azerbaigian 19
PY - Paraguay 18
SC - Seychelles 17
BY - Bielorussia 16
GP - Guadalupe 16
NO - Norvegia 15
SK - Slovacchia (Repubblica Slovacca) 15
CI - Costa d'Avorio 14
LB - Libano 12
OM - Oman 12
BB - Barbados 11
DO - Repubblica Dominicana 11
LU - Lussemburgo 11
NP - Nepal 11
HU - Ungheria 10
LK - Sri Lanka 10
UY - Uruguay 10
BH - Bahrain 8
LV - Lettonia 8
MU - Mauritius 8
PS - Palestinian Territory 8
Totale 143.699
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Città #
Ashburn 13.251
Southend 8.670
Seattle 5.341
Singapore 4.838
Fairfield 3.427
San Jose 2.674
Turin 2.582
Boardman 1.941
Chandler 1.911
Woodbridge 1.743
Ho Chi Minh City 1.524
Houston 1.469
Zhengzhou 1.400
Princeton 1.399
Hanoi 1.366
Council Bluffs 1.316
Jacksonville 1.287
Cambridge 1.261
Wilmington 1.194
Milan 1.191
Ann Arbor 1.134
Beijing 1.122
Santa Clara 1.110
Torino 1.105
Dublin 999
Hong Kong 931
Chicago 868
Izmir 833
Berlin 827
San Ramon 816
Dallas 764
Frankfurt 686
Herkenbosch 654
Bern 648
Moscow 619
Hefei 594
Los Angeles 561
Seoul 469
Helsinki 449
Tongling 444
Hangzhou 435
Lauterbourg 424
San Donato Milanese 419
Shanghai 408
Zaporozhye 351
Istanbul 334
Rome 322
Baltimore 319
Vienna 312
Pennsylvania Furnace 311
Des Moines 294
Saint Petersburg 289
Da Nang 278
New York 276
Overberg 268
Nuremberg 263
Buffalo 259
Bologna 253
Monopoli 242
Haiphong 221
Brussels 220
Mountain View 215
Bremen 197
Padua 196
Amsterdam 180
San Diego 168
Guangzhou 167
Toronto 162
Munich 154
São Paulo 154
Phoenix 149
San Francisco 147
The Dalles 143
Frankfurt am Main 140
North Bergen 138
Fremont 137
Redwood City 135
Jakarta 122
Malatya 119
Montreal 117
Groningen 115
Rotterdam 113
London 112
Columbus 108
Lecce 106
Tokyo 101
Falls Church 93
Miano 89
Norwalk 88
Ottawa 88
Washington 87
Dearborn 85
Brooklyn 80
Modena 77
Putian 75
Bangkok 74
Hải Dương 74
Atlanta 73
Melun 73
Wenzhou 70
Totale 86.637
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Nome #
Using Connectivity and Spectral Methods to Characterize the Structure of Sequential Logic Circuits 1.322
Data-Driven Clock Gating for Digital Filters 759
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 757
On-chip Thermal Modeling Based on SPICE Simulation 743
Modeling of thermally induced skew variations in clock distribution network 724
Memory Design Techniques for Low-Energy Embedded Systems 723
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 679
An on-chip all-digital PV-monitoring architecture for digital IPs 670
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 638
Aging Effects of Leakage Optimizations for Caches 626
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 607
GIS-Based Optimal Photovoltaic Panel Floorplanning for Residential Installations 602
Modeling of the Charging Behavior of Li-Ion Batteries based on Manufacturer’s Data 586
PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI 582
Fondamenti di Informatica: 100 Esercizi d'Esame Svolti 571
A Compact Macromodel for the Charge Phase of a Battery with Typical Charging Protocol 562
RTL Estimation of Steering Logic Power 545
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding 545
Buffering of frequent accesses for reduced cache aging 543
Approximate energy-efficient encoding for serial interfaces 539
A Low-Power Encoding Scheme for GigaByte Video Interfaces 526
Zero-Transition Serial Encoding for Image Sensors 523
A Top-down Constraint-driven Methodology for Smart System Design 517
Power Models for Semi-Autonomous RTL Macros 510
Partitioned cache architectures for reduced NBTI-induced aging 510
Power-Gating: More Than Leakage Savings 502
A Framework for Efficient Evaluation and Comparison of EES Models 491
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 490
A Compact PV Panel Model for Cyber-Physical Systems in Smart Cities 490
A Statistic Power Model for Non-synthetic RTL Operators 484
Energy-efficient digital processing via Approximate Computing 482
Fast thermal simulation using SystemC-AMS 482
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 473
Empirical derivation of upper and lower bounds of NBTI aging for embedded cores 470
An Efficient Simulation Methodology for Electrical Energy Systems 468
A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors 466
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Sub-Banking 466
Towards Multi-Domain and Multi-Physical Electronic Design 463
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting 454
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation 453
The Human Brain Project and Neuromorphic computing 445
An Open-Source Framework for Formal Specification and Simulation of Electrical Energy Systems 444
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 441
An equation-based battery cycle life model for various battery chemistries 441
A Smart Meter Infrastructure for Smart Grid IoT Applications 441
A Li-ion battery charge protocol with optimal aging-quality of service trade-off 440
Dynamic thermal clock skew compensation using tunable delay buffers 440
A Discrete-Time Battery Model for High-Level Power Estimation 439
Application of symbolic FSM Markovian analysis to protocol verification 436
A methodology for the design of dynamic accuracy operators by runtime back bias 435
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 435
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 434
Modeling and Simulation of the Power Flow in Smart Systems 433
A Framework with Temperature-Aware Accuracy Levels for Battery Modeling from Datasheets 431
An Automated Framework for Generating Variable-Accuracy Battery Models from Datasheet Information 431
Design Techniques and Architectures for Low-Leakage SRAMs 430
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 429
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns 426
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 425
Dual-Vt Assignment Policies in ITD-Aware Synthesis 424
An integrated thermal estimation framework for industrial embedded platforms 423
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 419
Automated generation of battery aging models from datasheets 417
An integrated thermal estimation framework for industrial embedded platforms. 413
A cosimulation methodology for HW/SW validation and performance estimation 412
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 412
Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces 409
Aging and cost optimal residential charging for plug-in EVs 409
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective 407
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits 405
Delay model for reconfigurable logic gates based on graphene PN-junctions 404
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 401
Discrete-time battery models for system-level low-power design 400
A refinement methodology for clock gating optimization at layout level in digital circuits 400
A Statistical Model of Cell-to-Cell Variation Li-ion Batteries for System-Level Design 400
Property verification of communication protocols based on probabilistic reachability analysis 399
Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology 399
Characterizing the activity factor in NBTI aging models for embedded cores 399
A temperature-aware battery cycle life model for different battery chemistries 399
Addressing the Smart Systems Design Challenge: The SMAC Platform 399
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 398
VHDL Simulation: A Flexible Approach to Verification and Performance Analysis of Communication Protocols 398
A unified model of power sources for the simulation of electrical energy systems 397
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 396
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 395
A Scalable Algorithmic Framework for Row-Based Power-Gating 394
A Fully Standard-Cell Delay Measurement Circuit for Timing Variability Detection 394
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 392
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 391
Battery-Aware Operation Range Estimation for Terrestrial and Aerial Electric Vehicles 384
Energy-optimal caches with guaranteed lifetime 382
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 381
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation 381
Glitch power minimization by selective gate freezing 380
Selective Instruction Compression for Memory Energy Reduction in Embedded Systems 380
Exploration of different implementation styles for graphene-based reconfigurable gates 379
A Machine Learning-based Digital Twin for Electric Vehicle Battery Modeling 379
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 378
Fast Computation of Discharge Current Upper Bounds for Clustered Power-Gating 377
Modeling of Physical Defects in PN-Junction Based Graphene Devices 376
Totale 47.601
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Categoria #
all - tutte 378.761
article - articoli 113.365
book - libri 4.861
conference - conferenze 248.264
curatela - curatele 0
other - altro 0
patent - brevetti 687
selected - selezionate 0
volume - volumi 11.385
Totale 757.323
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20223.778 0 0 0 0 176 384 237 209 170 449 832 1.321
2022/20237.682 743 1.239 251 652 804 964 744 378 681 107 294 825
2023/20242.557 177 226 236 125 241 276 150 174 61 127 268 496
2024/202513.354 184 1.359 738 1.703 733 543 854 1.304 2.035 785 805 2.311
2025/202630.389 1.724 1.168 1.792 2.456 1.560 1.562 4.034 2.566 6.835 4.121 947 1.624
2026/20278.231 843 1.072 1.956 3.542 818 0 0 0 0 0 0 0
Totale 144.738