In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting / Benini, I. L.; DE MICHELI, G.; Lioy, Antonio; Macii, Enrico; Odasso, G.; Poncino, Massimo. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 48:(1999), pp. 769-779. [10.1109/12.795120]

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting

LIOY, ANTONIO;MACII, Enrico;PONCINO, MASSIMO
1999

Abstract

In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/1404069
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