A Statistic Power Model for Non-synthetic RTL Operators

Power estimation at the Register-Transfer level is usually narrowed down to the problem of building accurate power models for the RTL (synthetic) operators. In this work we show that, when RTL power estimation is integrated into a realistic design flow, other types of primitives need to be accurately modeled. In particular, we show that most of the RTL functionality is realized by sparse logic elements. We thus propose statistical power models for these primitives, that we have validated on a set of industrial benchmarks.