MASERA, Guido
 Distribuzione geografica
Continente #
NA - Nord America 38.799
EU - Europa 31.398
AS - Asia 16.957
SA - Sud America 1.869
Continente sconosciuto - Info sul continente non disponibili 747
AF - Africa 382
OC - Oceania 24
-- - ???statistics.table.value.continent.--??? 2
Totale 90.178
Nazione #
US - Stati Uniti d'America 38.228
IT - Italia 7.934
FR - Francia 5.446
GB - Regno Unito 5.343
SG - Singapore 4.979
DE - Germania 4.894
VN - Vietnam 3.613
CN - Cina 3.472
RU - Federazione Russa 1.646
UA - Ucraina 1.603
BR - Brasile 1.456
NL - Olanda 955
KR - Corea 954
HK - Hong Kong 792
SE - Svezia 677
TR - Turchia 675
IN - India 633
IE - Irlanda 601
CH - Svizzera 531
FI - Finlandia 430
BD - Bangladesh 405
AT - Austria 358
CA - Canada 307
JP - Giappone 271
BE - Belgio 248
ID - Indonesia 166
AR - Argentina 127
PK - Pakistan 117
PH - Filippine 112
RO - Romania 110
TW - Taiwan 110
MY - Malesia 101
ES - Italia 98
IQ - Iraq 93
ZA - Sudafrica 90
MX - Messico 89
CL - Cile 86
PL - Polonia 85
TH - Thailandia 84
JO - Giordania 73
IL - Israele 70
SN - Senegal 66
IR - Iran 65
AP - ???statistics.table.value.countryCode.AP??? 63
EC - Ecuador 54
EU - Europa 53
GR - Grecia 51
JM - Giamaica 43
VE - Venezuela 41
CO - Colombia 40
MA - Marocco 39
DZ - Algeria 37
SA - Arabia Saudita 33
KE - Kenya 31
PT - Portogallo 30
AE - Emirati Arabi Uniti 28
CR - Costa Rica 27
CZ - Repubblica Ceca 26
TN - Tunisia 26
BG - Bulgaria 25
EG - Egitto 23
NI - Nicaragua 23
UZ - Uzbekistan 22
LT - Lituania 21
AU - Australia 19
ET - Etiopia 19
LU - Lussemburgo 19
PE - Perù 19
PY - Paraguay 19
LB - Libano 17
NG - Nigeria 17
EE - Estonia 15
NP - Nepal 15
TT - Trinidad e Tobago 15
AL - Albania 14
BO - Bolivia 13
HN - Honduras 13
NO - Norvegia 13
BY - Bielorussia 12
HR - Croazia 12
LV - Lettonia 12
UY - Uruguay 12
GT - Guatemala 11
HU - Ungheria 11
AZ - Azerbaigian 10
DK - Danimarca 10
OM - Oman 10
SV - El Salvador 10
DO - Repubblica Dominicana 9
QA - Qatar 8
SC - Seychelles 8
AM - Armenia 7
CI - Costa d'Avorio 7
KG - Kirghizistan 7
SK - Slovacchia (Repubblica Slovacca) 7
BA - Bosnia-Erzegovina 6
BB - Barbados 6
CY - Cipro 6
GE - Georgia 6
KW - Kuwait 6
Totale 89.349
Città #
Ashburn 8.753
Southend 4.677
Seattle 3.314
Fairfield 2.608
Singapore 2.560
San Jose 1.904
Turin 1.580
Chandler 1.321
Woodbridge 1.211
Ho Chi Minh City 992
Cambridge 979
Houston 979
Ann Arbor 916
Princeton 914
Wilmington 892
Jacksonville 867
Beijing 836
Hanoi 833
Boardman 729
Milan 699
Torino 657
Buffalo 634
Hong Kong 629
San Ramon 623
Santa Clara 620
Des Moines 609
Dublin 564
Berlin 539
Izmir 489
Council Bluffs 471
San Francisco 448
Bern 436
Chicago 436
Seoul 377
Los Angeles 369
Helsinki 360
Lauterbourg 356
Dallas 347
Herkenbosch 298
San Donato Milanese 262
Shanghai 262
Overland Park 254
Baltimore 236
Pennsylvania Furnace 234
Brussels 230
Rome 229
Zhengzhou 219
Overberg 207
Zaporozhye 207
Bologna 206
Saint Petersburg 190
North Bergen 187
Vienna 180
New York 174
Monopoli 171
Da Nang 170
Haiphong 140
San Diego 133
Amsterdam 131
Hefei 129
São Paulo 129
Padua 128
Norwalk 123
Guangzhou 119
Phoenix 119
Jakarta 116
Mountain View 116
Redwood City 115
Tokyo 113
Fuzhou 109
Hangzhou 109
Las Vegas 105
Atlanta 102
Columbus 97
Austin 96
Toronto 93
Frankfurt am Main 90
London 87
Munich 85
Moscow 84
Galati 79
Nuremberg 79
Paris 79
Shenzhen 78
The Dalles 75
Frankfurt 71
Malatya 71
Palermo 65
Fremont 64
Naples 63
Rotterdam 63
Orem 58
Clearwater 56
Genova 56
Melun 54
University Park 54
Lappeenranta 51
Modena 49
Groningen 48
Muizenberg 47
Totale 54.372
Nome #
Analysis of HEVC transform throughput requirements for hardware implementations 1.079
Introduzione all'analisi dei dispositivi a semiconduttore 961
EE-BESD: Molecular FET Modeling for Efficient and Effective Nanocomputing Design 793
Power Control for Crossbar-based Input-Queued Switches 680
Molecular transistor circuits: From device model to circuit simulation 666
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 666
Unequal Error Protection of memories in LDPC decoders 655
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders 632
Efficient VLSI Implementation of Soft-input Soft-output Fixed-complexity Sphere Decoder 619
Thermal control for crossbar-based input-queued switches 598
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 597
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 568
Unified turbo/LDPC code decoder architecture for deep-space communications 566
Comparison between HEVC and Thor based on objective and subjective assessments 563
A Network-on-Chip-based turbo/LDPC decoder architecture 561
Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes 557
Computation reduction for turbo decoding through window skipping 555
Adaptive Approximated DCT Architectures for HEVC 555
Reducing the dissipated energy in multi-standard turbo and LDPC decoders 549
Dispositivi e tecnologie elettroniche 548
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding 543
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator 543
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 529
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction 528
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 523
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 520
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 518
On optimal and near-optimal turbo decoding using generalized max operator 513
Clock distribution network optimization under self heating andtiming constraints 513
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 510
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 510
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 510
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 506
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 502
Introduzione all'analisi dei dispositivi a semiconduttore 500
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 498
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 496
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 488
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 485
Multiplierless Mumford and Shah Functional Implementation 478
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 476
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 473
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 462
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 460
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 459
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 454
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods 453
High speed architectures for finding the firsttwo maximum/minimum values 451
Scalable low-complexity B-spline discretewavelet transform architecture 449
On chip interconnects for multiprocessor turbo decoding architectures 442
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 438
Non-recursive max* operator with reduced implementation complexity for turbo decoding 438
Approximate Arai DCT Architecture for HEVC 434
Area Efficient DST Architectures for HEVC 430
State metric compression techniques for turbo decoder architectures 429
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 428
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 427
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 426
FFT implementation using QCA 424
A Flexible UMTS-WiMax Turbo Decoder Architecture 417
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 409
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization 405
Improving Network-on-Chip-based Turbo Decoder Architectures 404
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation 403
Encoded 16-PSK: A Study for the Receiver Design 398
"WindDesigner: An Open Tool for Analysis and Design of Wind Generators" 390
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) 386
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 382
Look--ahead Sphere Decoding: Algorithm and VLSI Architecture 377
Design of a VLSI Decoder for Partially Structured LDPC Codes 356
VLSI Architectures for WIMAX Channel Decoders 355
Mumford and Shah Functional: VLSI Analysis and Implementation 343
An LDPC Decoder Architecture forWireless Sensor Network Applications 343
MP-SoC/NoC Architectures for Error Correction 341
A new approach to compress the configuration information of programmable devices 341
VLSI architectures for turbo codes 339
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 337
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 337
A VLSI architecture for IWT (Integer Wavelet Transform) 336
Testing logic cores using a BIST P1500 compliant approach: a case of study 335
Design and implementation of a scalable multimedia processor 333
Beyond 3G Wireless Communication System Prototype 333
ASIP design for partially structured LDPC codes 332
A 2.63 Mbit/s VLSI implementation of SISO arithmetic decoders for high performance joint source channel codes 330
All digital VLSI fuzzy inference engine: a case study 328
ALOE-based flexible LDPC decoder 326
Low Resources Algorithm for Video Surveillance 322
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead 317
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 315
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study 314
A high accuracy-low complexity model for CMOS delays 311
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 309
Multiplierless, Folded 9/7 - 5/3 Wavelet VLSI Architecture 309
Architectural Strategies for Low-Power VLSI Turbo Decoders 308
A reduced clock swing domino gate in SOI 306
High throughput implementation of an adaptive serial concatenation turbo decoder 304
Finite precision implementationof LDPC decoders 302
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World 302
Coupled electro-thermal modeling and optimization of clock networks 301
System architecture for error-resilient, embedded JPEG2002 wireless delivery 300
Totale 45.670
Categoria #
all - tutte 238.014
article - articoli 92.083
book - libri 6.156
conference - conferenze 130.714
curatela - curatele 0
other - altro 0
patent - brevetti 1.340
selected - selezionate 0
volume - volumi 7.721
Totale 476.028


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20223.447 0 0 0 291 202 360 285 135 146 388 808 832
2022/20235.906 473 854 185 448 642 767 901 238 457 56 318 567
2023/20241.812 109 159 100 54 183 160 108 182 128 113 242 274
2024/20256.290 153 839 362 635 494 378 397 376 986 473 459 738
2025/202619.366 1.204 1.037 1.270 1.858 1.281 1.378 2.485 1.415 3.846 1.898 659 1.035
2026/20273.228 843 621 1.452 312 0 0 0 0 0 0 0 0
Totale 90.178