PORTO @ Archivio Istituzionale della Ricerca

MASERA, Guido
 Distribuzione geografica
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Continente #
NA - Nord America 30.740
EU - Europa 27.642
AS - Asia 4.835
AF - Africa 182
SA - Sud America 105
Continente sconosciuto - Info sul continente non disponibili 15
OC - Oceania 13
-- - ???statistics.table.value.continent.--??? 2
Totale 63.534
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Nazione #
US - Stati Uniti d'America 30.551
IT - Italia 6.745
GB - Regno Unito 5.229
FR - Francia 4.868
DE - Germania 4.662
CN - Cina 1.891
UA - Ucraina 1.572
SG - Singapore 866
NL - Olanda 857
RU - Federazione Russa 698
TR - Turchia 636
SE - Svezia 635
IE - Irlanda 587
CH - Svizzera 501
KR - Corea 466
FI - Finlandia 329
BE - Belgio 240
IN - India 180
CA - Canada 176
AT - Austria 163
HK - Hong Kong 159
JP - Giappone 120
ID - Indonesia 108
RO - Romania 102
MY - Malesia 80
AP - ???statistics.table.value.countryCode.AP??? 63
SN - Senegal 60
CL - Cile 54
PK - Pakistan 54
EU - Europa 53
IR - Iran 53
JO - Giordania 52
ZA - Sudafrica 51
IL - Israele 50
GR - Grecia 49
PL - Polonia 48
BR - Brasile 43
ES - Italia 43
VN - Vietnam 42
TW - Taiwan 38
BG - Bulgaria 24
CZ - Repubblica Ceca 22
DZ - Algeria 20
AE - Emirati Arabi Uniti 17
PT - Portogallo 17
LU - Lussemburgo 15
NG - Nigeria 15
LT - Lituania 14
MX - Messico 13
NO - Norvegia 13
EE - Estonia 12
HR - Croazia 11
TH - Thailandia 10
AU - Australia 9
PH - Filippine 9
SA - Arabia Saudita 9
EG - Egitto 8
HU - Ungheria 8
SC - Seychelles 8
DK - Danimarca 7
IQ - Iraq 6
LV - Lettonia 6
A2 - ???statistics.table.value.countryCode.A2??? 5
BY - Bielorussia 5
SK - Slovacchia (Repubblica Slovacca) 5
TN - Tunisia 5
UZ - Uzbekistan 5
BA - Bosnia-Erzegovina 4
CI - Costa d'Avorio 4
LB - Libano 4
NZ - Nuova Zelanda 4
AL - Albania 3
GH - Ghana 3
MA - Marocco 3
RS - Serbia 3
A1 - Anonimo 2
AR - Argentina 2
BD - Bangladesh 2
CO - Colombia 2
CY - Cipro 2
EC - Ecuador 2
ET - Etiopia 2
KZ - Kazakistan 2
ME - Montenegro 2
AM - Armenia 1
AZ - Azerbaigian 1
KH - Cambogia 1
KW - Kuwait 1
LK - Sri Lanka 1
MD - Moldavia 1
MT - Malta 1
MZ - Mozambico 1
NP - Nepal 1
PY - Paraguay 1
QA - Qatar 1
SI - Slovenia 1
SY - Repubblica araba siriana 1
TG - Togo 1
VE - Venezuela 1
ZW - Zimbabwe 1
Totale 63.534
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Città #
Ashburn 7.236
Southend 4.677
Seattle 3.294
Fairfield 2.606
Chandler 1.320
Turin 1.235
Woodbridge 1.208
Cambridge 976
Houston 964
Ann Arbor 916
Princeton 914
Wilmington 887
Jacksonville 856
Boardman 689
Torino 657
Singapore 630
San Ramon 623
Des Moines 601
Beijing 567
Dublin 554
Berlin 537
Buffalo 514
Izmir 489
Milan 484
Santa Clara 461
Bern 436
San Francisco 425
Helsinki 302
Herkenbosch 298
Chicago 286
San Donato Milanese 262
Overland Park 254
Pennsylvania Furnace 234
Brussels 227
Shanghai 224
Baltimore 211
Overberg 207
Zaporozhye 207
Zhengzhou 205
Saint Petersburg 190
Bologna 187
Monopoli 171
Vienna 154
Council Bluffs 143
Rome 134
San Diego 128
Padua 125
Norwalk 123
Mountain View 116
Redwood City 115
Hong Kong 109
Amsterdam 108
Fuzhou 108
San Jose 108
Hangzhou 105
Jakarta 105
Austin 95
Las Vegas 92
Guangzhou 87
Galati 79
Atlanta 73
Seoul 72
Frankfurt 71
Malatya 71
Shenzhen 70
Toronto 68
Columbus 67
Fremont 64
Paris 63
Rotterdam 63
London 62
New York 62
Phoenix 62
Genova 56
Clearwater 55
Melun 54
Palermo 54
University Park 54
Modena 48
Muizenberg 47
Munich 46
Cupertino 43
San Mateo 42
Indiana 40
Dallas 39
Henderson 39
Andover 37
Podenzano 37
Dearborn 36
Istanbul 36
Yubileyny 36
Verona 35
Putian 34
Lecce 32
Nanjing 32
Ningbo 32
Falls Church 29
Gilroy 29
Lausanne 29
Menlo Park 29
Totale 42.203
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Nome #
Introduzione all'analisi dei dispositivi a semiconduttore 842
Analysis of HEVC transform throughput requirements for hardware implementations 675
EE-BESD: Molecular FET Modeling for Efficient and Effective Nanocomputing Design 653
Molecular transistor circuits: From device model to circuit simulation 553
Power Control for Crossbar-based Input-Queued Switches 525
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 517
Unequal Error Protection of memories in LDPC decoders 497
Efficient VLSI Implementation of Soft-input Soft-output Fixed-complexity Sphere Decoder 481
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 473
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders 471
Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes 458
Thermal control for crossbar-based input-queued switches 455
Dispositivi e tecnologie elettroniche 454
Comparison between HEVC and Thor based on objective and subjective assessments 444
A Network-on-Chip-based turbo/LDPC decoder architecture 443
Clock distribution network optimization under self heating andtiming constraints 442
Introduzione all'analisi dei dispositivi a semiconduttore 441
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction 439
Unified turbo/LDPC code decoder architecture for deep-space communications 436
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 436
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 432
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 431
Computation reduction for turbo decoding through window skipping 430
Reducing the dissipated energy in multi-standard turbo and LDPC decoders 426
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 424
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 417
Adaptive Approximated DCT Architectures for HEVC 416
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 416
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 415
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding 413
On optimal and near-optimal turbo decoding using generalized max operator 410
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 402
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 396
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 396
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 392
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 389
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 389
Multiplierless Mumford and Shah Functional Implementation 387
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 385
Scalable low-complexity B-spline discretewavelet transform architecture 382
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 378
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 375
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator 371
High speed architectures for finding the firsttwo maximum/minimum values 365
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 361
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 358
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 352
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 352
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 350
Non-recursive max* operator with reduced implementation complexity for turbo decoding 350
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 349
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 348
On chip interconnects for multiprocessor turbo decoding architectures 344
A Flexible UMTS-WiMax Turbo Decoder Architecture 340
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 339
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods 337
Area Efficient DST Architectures for HEVC 333
Approximate Arai DCT Architecture for HEVC 331
State metric compression techniques for turbo decoder architectures 327
Encoded 16-PSK: A Study for the Receiver Design 316
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 315
Improving Network-on-Chip-based Turbo Decoder Architectures 315
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization 312
Look--ahead Sphere Decoding: Algorithm and VLSI Architecture 306
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation 306
FFT implementation using QCA 300
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 296
"WindDesigner: An Open Tool for Analysis and Design of Wind Generators" 296
VLSI Architectures for WIMAX Channel Decoders 286
A VLSI architecture for IWT (Integer Wavelet Transform) 277
A new approach to compress the configuration information of programmable devices 273
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 267
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 264
All digital VLSI fuzzy inference engine: a case study 264
Mumford and Shah Functional: VLSI Analysis and Implementation 261
Low Resources Algorithm for Video Surveillance 261
A high accuracy-low complexity model for CMOS delays 260
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 260
Beyond 3G Wireless Communication System Prototype 259
ASIP design for partially structured LDPC codes 258
MP-SoC/NoC Architectures for Error Correction 257
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 257
Testing logic cores using a BIST P1500 compliant approach: a case of study 257
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study 252
Design and implementation of a scalable multimedia processor 251
System architecture for error-resilient, embedded JPEG2002 wireless delivery 250
A 2.63 Mbit/s VLSI implementation of SISO arithmetic decoders for high performance joint source channel codes 250
An LDPC Decoder Architecture forWireless Sensor Network Applications 248
Coupled electro-thermal modeling and optimization of clock networks 247
A reduced clock swing domino gate in SOI 247
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications 244
ALOE-based flexible LDPC decoder 244
VLSI architectures for turbo codes 244
High throughput implementation of an adaptive serial concatenation turbo decoder 244
Design of a VLSI Decoder for Partially Structured LDPC Codes 241
Architectural Strategies for Low-Power VLSI Turbo Decoders 239
Comparative analysis of PD-SOI Active Body-Biasing Circuits 237
Decoding the Golden space-time trellis codedmodulation 235
FPGA Power Efficient Inverse Lifting Wavelet IP 234
A VLSI processor array for graph isomorphism 228
Totale 35.801
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Categoria #
all - tutte 165.809
article - articoli 64.214
book - libri 4.863
conference - conferenze 90.396
curatela - curatele 0
other - altro 0
patent - brevetti 865
selected - selezionate 0
volume - volumi 5.471
Totale 331.618
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20203.489 0 0 0 0 0 0 826 924 893 399 308 139
2020/20215.060 602 754 271 586 313 475 210 426 306 537 342 238
2021/20224.025 213 269 96 291 202 360 285 135 146 388 808 832
2022/20235.906 473 854 185 448 642 767 901 238 457 56 318 567
2023/20241.812 109 159 100 54 183 160 108 182 128 113 242 274
2024/20252.863 153 839 362 635 494 378 2 0 0 0 0 0
Totale 64.157