PORTO @ Archivio Istituzionale della Ricerca

MASERA, Guido
 Distribuzione geografica
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Continente #
NA - Nord America 32.217
EU - Europa 28.605
AS - Asia 8.227
SA - Sud America 1.115
AF - Africa 247
OC - Oceania 17
Continente sconosciuto - Info sul continente non disponibili 15
-- - ???statistics.table.value.continent.--??? 2
Totale 70.445
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Nazione #
US - Stati Uniti d'America 31.961
IT - Italia 7.032
GB - Regno Unito 5.267
FR - Francia 5.017
DE - Germania 4.789
CN - Cina 2.861
SG - Singapore 2.341
UA - Ucraina 1.587
BR - Brasile 932
NL - Olanda 881
KR - Corea 741
RU - Federazione Russa 725
TR - Turchia 664
SE - Svezia 643
IE - Irlanda 596
CH - Svizzera 516
FI - Finlandia 350
AT - Austria 335
HK - Hong Kong 319
VN - Vietnam 244
BE - Belgio 242
IN - India 233
CA - Canada 193
JP - Giappone 148
ID - Indonesia 121
RO - Romania 106
MY - Malesia 82
PK - Pakistan 75
PL - Polonia 69
CL - Cile 64
AP - ???statistics.table.value.countryCode.AP??? 63
IL - Israele 61
SN - Senegal 61
ZA - Sudafrica 61
ES - Italia 57
IR - Iran 55
JO - Giordania 54
EU - Europa 53
BD - Bangladesh 50
GR - Grecia 50
AR - Argentina 48
TW - Taiwan 41
MX - Messico 36
IQ - Iraq 32
EC - Ecuador 29
DZ - Algeria 28
BG - Bulgaria 24
CZ - Repubblica Ceca 24
AE - Emirati Arabi Uniti 22
PT - Portogallo 21
MA - Marocco 20
SA - Arabia Saudita 20
LU - Lussemburgo 19
LT - Lituania 16
NG - Nigeria 15
EE - Estonia 13
KE - Kenya 13
NO - Norvegia 13
TH - Thailandia 13
UZ - Uzbekistan 13
AU - Australia 12
EG - Egitto 11
HR - Croazia 11
PH - Filippine 11
TN - Tunisia 11
VE - Venezuela 11
CO - Colombia 10
BY - Bielorussia 9
DK - Danimarca 9
HU - Ungheria 9
LV - Lettonia 9
SC - Seychelles 8
LB - Libano 7
NP - Nepal 7
PY - Paraguay 7
AL - Albania 6
SK - Slovacchia (Repubblica Slovacca) 6
UY - Uruguay 6
A2 - ???statistics.table.value.countryCode.A2??? 5
BA - Bosnia-Erzegovina 5
BH - Bahrain 5
CI - Costa d'Avorio 5
DO - Repubblica Dominicana 5
JM - Giamaica 5
PE - Perù 5
TT - Trinidad e Tobago 5
AZ - Azerbaigian 4
CY - Cipro 4
ET - Etiopia 4
GE - Georgia 4
NI - Nicaragua 4
NZ - Nuova Zelanda 4
QA - Qatar 4
BN - Brunei Darussalam 3
BO - Bolivia 3
GH - Ghana 3
KG - Kirghizistan 3
KW - Kuwait 3
KZ - Kazakistan 3
RS - Serbia 3
Totale 70.408
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Città #
Ashburn 7.607
Southend 4.677
Seattle 3.299
Fairfield 2.606
Turin 1.382
Chandler 1.320
Woodbridge 1.208
Singapore 1.163
Cambridge 977
Houston 964
Ann Arbor 916
Princeton 914
Wilmington 887
Jacksonville 858
Beijing 731
Boardman 709
Torino 657
San Ramon 623
Des Moines 601
Buffalo 589
Dublin 560
Berlin 537
Milan 514
Izmir 489
Santa Clara 469
San Francisco 437
Bern 436
Helsinki 306
Herkenbosch 298
Chicago 294
Dallas 277
San Donato Milanese 262
Hong Kong 261
Overland Park 254
Shanghai 245
Pennsylvania Furnace 234
Brussels 229
Council Bluffs 221
Seoul 217
Zhengzhou 215
Baltimore 211
Overberg 207
Zaporozhye 207
Bologna 192
Saint Petersburg 190
Monopoli 171
Vienna 171
Rome 149
San Diego 129
Padua 125
Norwalk 123
Mountain View 116
Redwood City 115
Amsterdam 114
San Jose 111
Guangzhou 110
Fuzhou 109
Jakarta 109
Hangzhou 107
Los Angeles 107
Ho Chi Minh City 105
Hefei 103
Austin 96
Las Vegas 93
Columbus 87
Atlanta 80
Galati 79
New York 79
Paris 72
Frankfurt 71
Malatya 71
Shenzhen 71
Toronto 70
São Paulo 69
Munich 68
Nuremberg 67
London 65
Fremont 64
Phoenix 64
Rotterdam 63
Genova 56
Clearwater 55
Melun 54
Palermo 54
University Park 54
Modena 48
Muizenberg 47
Cupertino 43
Istanbul 43
San Mateo 42
Hanoi 41
Frankfurt am Main 40
Indiana 40
Henderson 39
Islamabad 39
Andover 37
Nanjing 37
Podenzano 37
Dearborn 36
Tokyo 36
Totale 44.731
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Nome #
Introduzione all'analisi dei dispositivi a semiconduttore 873
Analysis of HEVC transform throughput requirements for hardware implementations 758
EE-BESD: Molecular FET Modeling for Efficient and Effective Nanocomputing Design 705
Molecular transistor circuits: From device model to circuit simulation 589
Power Control for Crossbar-based Input-Queued Switches 576
Unequal Error Protection of memories in LDPC decoders 541
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 535
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders 516
Efficient VLSI Implementation of Soft-input Soft-output Fixed-complexity Sphere Decoder 514
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 514
Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes 489
Thermal control for crossbar-based input-queued switches 488
Comparison between HEVC and Thor based on objective and subjective assessments 472
Dispositivi e tecnologie elettroniche 469
A Network-on-Chip-based turbo/LDPC decoder architecture 467
Unified turbo/LDPC code decoder architecture for deep-space communications 465
Computation reduction for turbo decoding through window skipping 464
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction 462
Introduzione all'analisi dei dispositivi a semiconduttore 457
Clock distribution network optimization under self heating andtiming constraints 456
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 455
Reducing the dissipated energy in multi-standard turbo and LDPC decoders 453
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 451
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 451
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 445
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 444
Adaptive Approximated DCT Architectures for HEVC 443
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 441
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 441
On optimal and near-optimal turbo decoding using generalized max operator 434
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding 434
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 427
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 424
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 423
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 422
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 419
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator 419
Multiplierless Mumford and Shah Functional Implementation 415
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 414
Scalable low-complexity B-spline discretewavelet transform architecture 405
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 403
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 396
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 394
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 391
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 385
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 385
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 383
High speed architectures for finding the firsttwo maximum/minimum values 383
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 380
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 378
Non-recursive max* operator with reduced implementation complexity for turbo decoding 375
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 372
On chip interconnects for multiprocessor turbo decoding architectures 364
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods 360
A Flexible UMTS-WiMax Turbo Decoder Architecture 358
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 357
State metric compression techniques for turbo decoder architectures 357
Area Efficient DST Architectures for HEVC 356
Approximate Arai DCT Architecture for HEVC 355
Encoded 16-PSK: A Study for the Receiver Design 348
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation 341
Improving Network-on-Chip-based Turbo Decoder Architectures 336
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 330
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization 329
Look--ahead Sphere Decoding: Algorithm and VLSI Architecture 324
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 322
"WindDesigner: An Open Tool for Analysis and Design of Wind Generators" 320
FFT implementation using QCA 317
VLSI Architectures for WIMAX Channel Decoders 302
A VLSI architecture for IWT (Integer Wavelet Transform) 293
A new approach to compress the configuration information of programmable devices 292
Beyond 3G Wireless Communication System Prototype 286
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 286
Mumford and Shah Functional: VLSI Analysis and Implementation 285
MP-SoC/NoC Architectures for Error Correction 280
Testing logic cores using a BIST P1500 compliant approach: a case of study 279
A high accuracy-low complexity model for CMOS delays 276
Design and implementation of a scalable multimedia processor 276
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 276
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 276
Low Resources Algorithm for Video Surveillance 276
ASIP design for partially structured LDPC codes 275
A 2.63 Mbit/s VLSI implementation of SISO arithmetic decoders for high performance joint source channel codes 271
VLSI architectures for turbo codes 271
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 271
All digital VLSI fuzzy inference engine: a case study 271
An LDPC Decoder Architecture forWireless Sensor Network Applications 269
ALOE-based flexible LDPC decoder 268
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study 266
Coupled electro-thermal modeling and optimization of clock networks 264
Design of a VLSI Decoder for Partially Structured LDPC Codes 262
Architectural Strategies for Low-Power VLSI Turbo Decoders 260
High throughput implementation of an adaptive serial concatenation turbo decoder 260
System architecture for error-resilient, embedded JPEG2002 wireless delivery 259
A reduced clock swing domino gate in SOI 259
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications 256
Decoding the Golden space-time trellis codedmodulation 252
A VLSI processor array for graph isomorphism 250
Comparative analysis of PD-SOI Active Body-Biasing Circuits 246
dynDCT: a dynamically adaptable integer DCT 243
Totale 38.225
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Categoria #
all - tutte 191.215
article - articoli 74.206
book - libri 5.326
conference - conferenze 104.389
curatela - curatele 0
other - altro 0
patent - brevetti 1.025
selected - selezionate 0
volume - volumi 6.269
Totale 382.430
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20213.433 0 0 0 586 313 475 210 426 306 537 342 238
2021/20224.025 213 269 96 291 202 360 285 135 146 388 808 832
2022/20235.906 473 854 185 448 642 767 901 238 457 56 318 567
2023/20241.812 109 159 100 54 183 160 108 182 128 113 242 274
2024/20256.290 153 839 362 635 494 378 397 376 986 473 459 738
2025/20263.535 1.204 1.037 1.270 24 0 0 0 0 0 0 0 0
Totale 71.119