PORTO @ Archivio Istituzionale della Ricerca

MASERA, Guido
 Distribuzione geografica
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Continente #
NA - Nord America 30.205
EU - Europa 27.155
AS - Asia 4.260
AF - Africa 180
SA - Sud America 95
Continente sconosciuto - Info sul continente non disponibili 15
OC - Oceania 12
-- - ???statistics.table.value.continent.--??? 2
Totale 61.924
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Nazione #
US - Stati Uniti d'America 30.028
IT - Italia 6.647
GB - Regno Unito 5.212
FR - Francia 4.851
DE - Germania 4.619
CN - Cina 1.824
UA - Ucraina 1.571
NL - Olanda 853
SG - Singapore 638
SE - Svezia 635
TR - Turchia 605
IE - Irlanda 586
CH - Svizzera 501
RU - Federazione Russa 459
KR - Corea 353
FI - Finlandia 317
BE - Belgio 194
IN - India 180
CA - Canada 164
AT - Austria 161
HK - Hong Kong 135
JP - Giappone 119
RO - Romania 102
MY - Malesia 77
AP - ???statistics.table.value.countryCode.AP??? 63
SN - Senegal 60
CL - Cile 54
EU - Europa 53
IR - Iran 53
PK - Pakistan 53
JO - Giordania 52
ZA - Sudafrica 50
GR - Grecia 49
IL - Israele 49
PL - Polonia 47
ES - Italia 43
VN - Vietnam 42
TW - Taiwan 37
BR - Brasile 35
BG - Bulgaria 24
CZ - Repubblica Ceca 22
DZ - Algeria 20
AE - Emirati Arabi Uniti 17
PT - Portogallo 17
LU - Lussemburgo 15
NG - Nigeria 15
MX - Messico 13
NO - Norvegia 13
EE - Estonia 12
HR - Croazia 11
TH - Thailandia 10
AU - Australia 9
PH - Filippine 9
SA - Arabia Saudita 9
EG - Egitto 8
HU - Ungheria 8
LT - Lituania 8
SC - Seychelles 8
DK - Danimarca 7
ID - Indonesia 6
LV - Lettonia 6
A2 - ???statistics.table.value.countryCode.A2??? 5
BY - Bielorussia 5
IQ - Iraq 5
SK - Slovacchia (Repubblica Slovacca) 5
TN - Tunisia 5
BA - Bosnia-Erzegovina 4
CI - Costa d'Avorio 4
LB - Libano 4
UZ - Uzbekistan 4
AL - Albania 3
GH - Ghana 3
MA - Marocco 3
NZ - Nuova Zelanda 3
RS - Serbia 3
A1 - Anonimo 2
AR - Argentina 2
BD - Bangladesh 2
CY - Cipro 2
EC - Ecuador 2
ET - Etiopia 2
KZ - Kazakistan 2
ME - Montenegro 2
AM - Armenia 1
AZ - Azerbaigian 1
CO - Colombia 1
KH - Cambogia 1
KW - Kuwait 1
LK - Sri Lanka 1
MD - Moldavia 1
MT - Malta 1
MZ - Mozambico 1
QA - Qatar 1
SI - Slovenia 1
SY - Repubblica araba siriana 1
VE - Venezuela 1
ZW - Zimbabwe 1
Totale 61.924
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Città #
Ashburn 7.198
Southend 4.677
Seattle 3.293
Fairfield 2.606
Chandler 1.320
Woodbridge 1.208
Turin 1.198
Cambridge 976
Houston 964
Ann Arbor 916
Princeton 914
Wilmington 887
Jacksonville 856
Boardman 689
Torino 657
San Ramon 623
Des Moines 601
Beijing 566
Dublin 553
Berlin 537
Buffalo 514
Izmir 489
Milan 474
Singapore 441
Bern 436
San Francisco 425
Herkenbosch 298
Helsinki 290
Chicago 286
San Donato Milanese 262
Overland Park 254
Pennsylvania Furnace 234
Shanghai 222
Baltimore 211
Overberg 207
Zaporozhye 207
Zhengzhou 205
Saint Petersburg 190
Bologna 187
Brussels 181
Monopoli 171
Vienna 153
Council Bluffs 129
San Diego 128
Rome 126
Padua 125
Norwalk 123
Mountain View 116
Redwood City 115
Fuzhou 108
San Jose 108
Amsterdam 107
Hangzhou 105
Austin 95
Las Vegas 92
Guangzhou 86
Hong Kong 86
Galati 79
Atlanta 73
Frankfurt 71
Malatya 71
Seoul 71
Shenzhen 70
Columbus 67
Fremont 64
Rotterdam 63
New York 62
Phoenix 62
Paris 60
Toronto 58
Genova 56
Clearwater 55
Melun 54
University Park 54
London 53
Palermo 52
Santa Clara 52
Modena 48
Muizenberg 47
Cupertino 43
San Mateo 42
Indiana 40
Dallas 39
Henderson 39
Andover 37
Podenzano 37
Dearborn 36
Verona 35
Putian 34
Lecce 32
Nanjing 32
Ningbo 32
Falls Church 29
Gilroy 29
Lausanne 29
Menlo Park 29
Islamabad 28
Munich 28
Kuala Lumpur 27
Los Angeles 26
Totale 41.270
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Nome #
Introduzione all'analisi dei dispositivi a semiconduttore 819
Analysis of HEVC transform throughput requirements for hardware implementations 665
EE-BESD: Molecular FET Modeling for Efficient and Effective Nanocomputing Design 641
Molecular transistor circuits: From device model to circuit simulation 540
Power Control for Crossbar-based Input-Queued Switches 518
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 512
Unequal Error Protection of memories in LDPC decoders 487
Efficient VLSI Implementation of Soft-input Soft-output Fixed-complexity Sphere Decoder 470
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 462
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders 461
Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes 455
Dispositivi e tecnologie elettroniche 452
Thermal control for crossbar-based input-queued switches 447
Clock distribution network optimization under self heating andtiming constraints 440
Introduzione all'analisi dei dispositivi a semiconduttore 436
Comparison between HEVC and Thor based on objective and subjective assessments 436
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction 436
A Network-on-Chip-based turbo/LDPC decoder architecture 436
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 431
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 428
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 426
Computation reduction for turbo decoding through window skipping 426
Unified turbo/LDPC code decoder architecture for deep-space communications 425
Reducing the dissipated energy in multi-standard turbo and LDPC decoders 423
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 418
Adaptive Approximated DCT Architectures for HEVC 410
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 409
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding 408
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 408
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 408
On optimal and near-optimal turbo decoding using generalized max operator 407
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 396
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 392
Multiplierless Mumford and Shah Functional Implementation 386
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 385
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 384
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 384
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 381
Scalable low-complexity B-spline discretewavelet transform architecture 380
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 376
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 374
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 369
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator 363
High speed architectures for finding the firsttwo maximum/minimum values 362
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 353
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 351
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 350
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 349
Non-recursive max* operator with reduced implementation complexity for turbo decoding 346
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 345
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 343
On chip interconnects for multiprocessor turbo decoding architectures 342
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 341
A Flexible UMTS-WiMax Turbo Decoder Architecture 334
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods 333
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 331
Area Efficient DST Architectures for HEVC 328
Approximate Arai DCT Architecture for HEVC 326
State metric compression techniques for turbo decoder architectures 324
Improving Network-on-Chip-based Turbo Decoder Architectures 313
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 312
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization 309
Encoded 16-PSK: A Study for the Receiver Design 308
Look--ahead Sphere Decoding: Algorithm and VLSI Architecture 301
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation 301
FFT implementation using QCA 294
"WindDesigner: An Open Tool for Analysis and Design of Wind Generators" 293
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 285
VLSI Architectures for WIMAX Channel Decoders 284
A VLSI architecture for IWT (Integer Wavelet Transform) 275
A new approach to compress the configuration information of programmable devices 266
All digital VLSI fuzzy inference engine: a case study 261
A high accuracy-low complexity model for CMOS delays 259
Mumford and Shah Functional: VLSI Analysis and Implementation 259
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 259
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 258
Effects of Temperature in Deep-Submicron Global Interconnect Optimization 256
Beyond 3G Wireless Communication System Prototype 254
MP-SoC/NoC Architectures for Error Correction 253
Low Resources Algorithm for Video Surveillance 253
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 251
ASIP design for partially structured LDPC codes 250
Testing logic cores using a BIST P1500 compliant approach: a case of study 249
System architecture for error-resilient, embedded JPEG2002 wireless delivery 248
A 2.63 Mbit/s VLSI implementation of SISO arithmetic decoders for high performance joint source channel codes 247
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study 245
Design and implementation of a scalable multimedia processor 244
Coupled electro-thermal modeling and optimization of clock networks 244
A reduced clock swing domino gate in SOI 244
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications 243
An LDPC Decoder Architecture forWireless Sensor Network Applications 241
Architectural Strategies for Low-Power VLSI Turbo Decoders 237
High throughput implementation of an adaptive serial concatenation turbo decoder 236
ALOE-based flexible LDPC decoder 235
Comparative analysis of PD-SOI Active Body-Biasing Circuits 235
VLSI architectures for turbo codes 234
Decoding the Golden space-time trellis codedmodulation 232
FPGA Power Efficient Inverse Lifting Wavelet IP 230
Design of a VLSI Decoder for Partially Structured LDPC Codes 230
A VLSI processor array for graph isomorphism 226
Totale 35.222
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Categoria #
all - tutte 156.870
article - articoli 60.735
book - libri 4.669
conference - conferenze 85.521
curatela - curatele 0
other - altro 0
patent - brevetti 806
selected - selezionate 0
volume - volumi 5.139
Totale 313.740
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20206.536 0 0 337 922 974 814 826 924 893 399 308 139
2020/20215.060 602 754 271 586 313 475 210 426 306 537 342 238
2021/20224.025 213 269 96 291 202 360 285 135 146 388 808 832
2022/20235.906 473 854 185 448 642 767 901 238 457 56 318 567
2023/20241.812 109 159 100 54 183 160 108 182 128 113 242 274
2024/20251.241 155 842 244 0 0 0 0 0 0 0 0 0
Totale 62.535