The resistance of on-chip interconnects and the current drive of transistors are strongly temperature-dependent. As a result, the interconnect performance in Deep-Submicron technologies is affected by temperature in a substantial proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure based on repeaters insertion. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future CMOS technologies, according to the semiconductor roadmap.
|Titolo:||Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes|
|Data di pubblicazione:||2004|
|Digital Object Identifier (DOI):||10.1016/j.mejo.2004.06.017|
|Appare nelle tipologie:||1.1 Articolo in rivista|