Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input max∗ approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10e−5, assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity.
|Titolo:||Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures|
|Data di pubblicazione:||2014|
|Digital Object Identifier (DOI):||10.1109/TIM.2013.2281554|
|Appare nelle tipologie:||1.1 Articolo in rivista|