Archivio Istituzionale della RicercaIn this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. The obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. Logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications / Martina, Maurizio; Masera, Guido; Piccinini, Gianluca; Vacca, F.; Zamboni, Maurizio. - STAMPA. - (2001), pp. 347-351. (Intervento presentato al convegno IEEE International Conference on ASIC/SOC tenutosi a Arlington, USA nel September 2001) [10.1109/ASIC.2001.954725].
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications
MARTINA, MAURIZIO;MASERA, Guido;PICCININI, GIANLUCA;ZAMBONI, Maurizio
2001
Abstract
In this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. The obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. Logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells
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https://hdl.handle.net/11583/1419307
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