Archivio Istituzionale della RicercaThe authors have introduced a domino gate that operates at a reduced clock swing. Using a DTMOS, the performance degradation is minimal while the total power consumption is greatly reduced since the clock tree has a halved voltage swing. Due to the squared relationship between voltage and power, 75% saving can be obtained on a clock whose contribution can be up to 50% of the overall power consumption. The use of active body-biasing circuits yields an order of magnitude reduction of the gate leakage power dissipation.
A reduced clock swing domino gate in SOI / Casu, MARIO ROBERTO; Gelmi, M.; Masera, Guido; Piccinini, Gianluca; Zamboni, Maurizio. - (2002), pp. 91-92. (Intervento presentato al convegno IEEE International Silicon-on-Insulator (SOI) Conference tenutosi a Williamsburg (USA) nel 7-10 October 2002) [10.1109/SOI.2002.1044430].
A reduced clock swing domino gate in SOI
CASU, MARIO ROBERTO;MASERA, Guido;PICCININI, GIANLUCA;ZAMBONI, Maurizio
2002
Abstract
The authors have introduced a domino gate that operates at a reduced clock swing. Using a DTMOS, the performance degradation is minimal while the total power consumption is greatly reduced since the clock tree has a halved voltage swing. Due to the squared relationship between voltage and power, 75% saving can be obtained on a clock whose contribution can be up to 50% of the overall power consumption. The use of active body-biasing circuits yields an order of magnitude reduction of the gate leakage power dissipation.
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https://hdl.handle.net/11583/1410360
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