In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper.
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction / CASU M.R.; GRAZIANO M.; MASERA G.; PICCININI G.; ZAMBONI M.. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - STAMPA. - 12(2004), pp. 349-358. [10.1109/TVLSI.2004.825599]
|Titolo:||An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction|
|Data di pubblicazione:||2004|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/TVLSI.2004.825599|
|Appare nelle tipologie:||1.1 Articolo in rivista|