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EnglishThe current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology.
A Network-on-Chip-based turbo/LDPC decoder architecture / Condo C.; Martina M.; Masera G.. - STAMPA. - (2012), pp. 1525-1530. ((Intervento presentato al convegno Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 tenutosi a Dresden (D) nel 12-16 Mar. 2012 [10.1109/DATE.2012.6176715].
| Titolo: | A Network-on-Chip-based turbo/LDPC decoder architecture | |
| Autori: | ||
| Data di pubblicazione: | 2012 | |
| Abstract: | The current convergence process in wireless technologies demands for strong efforts in the concei...ving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology. | |
| ISBN: | 9781457721458 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| DATE 2012.pdf | 1. Preprint / submitted version [pre- review] | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri | |
| 06176715.pdf | 2. Post-print / Author's Accepted Manuscript | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2496859
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