Analysis of HEVC transform throughput requirements for hardware implementations

Hardware implementations can provide significant speedup and saving for video compression applications. In this work we focus on the transform coding sub-module analyzing the performance required by actual encoder implementations. We show that the throughput assumption about the transform sub-module in most research works is overly optimistic since it does not consider the complexity of a rate-distortion optimized video coding process. Many HEVC coding options are compared in terms of impact on quality and throughput, so to recommend the most efficient settings without excessively penalizing quality. Moreover, comparisons with the AVC standard show that, in general, HEVC presents much higher complexity to deliver its claimed compression advantages. Finally, a practical case study is shown to highlight how the proposed transform throughput analysis could be used to determine the throughput for a transform sub-module hardware design.