PORTO @ Archivio Istituzionale della Ricerca

MARTINA, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 17.784
EU - Europa 15.159
AS - Asia 2.509
AF - Africa 135
SA - Sud America 70
OC - Oceania 13
Continente sconosciuto - Info sul continente non disponibili 10
Totale 35.680
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Nazione #
US - Stati Uniti d'America 17.620
IT - Italia 4.025
GB - Regno Unito 2.973
DE - Germania 2.595
FR - Francia 2.356
CN - Cina 1.131
UA - Ucraina 698
IE - Irlanda 405
NL - Olanda 375
SE - Svezia 294
RU - Federazione Russa 290
CH - Svizzera 285
TR - Turchia 284
SG - Singapore 234
KR - Corea 192
BE - Belgio 189
FI - Finlandia 171
HK - Hong Kong 162
IN - India 162
CA - Canada 156
RO - Romania 82
AT - Austria 74
JP - Giappone 57
SN - Senegal 57
MY - Malesia 51
GR - Grecia 46
PK - Pakistan 43
ES - Italia 42
BG - Bulgaria 40
ZA - Sudafrica 38
AP - ???statistics.table.value.countryCode.AP??? 37
CL - Cile 37
IR - Iran 37
IL - Israele 34
PL - Polonia 33
VN - Vietnam 31
JO - Giordania 30
BR - Brasile 28
EU - Europa 23
TW - Taiwan 23
CZ - Repubblica Ceca 19
EE - Estonia 14
PT - Portogallo 14
AE - Emirati Arabi Uniti 13
NO - Norvegia 13
DK - Danimarca 10
HR - Croazia 10
LU - Lussemburgo 10
AU - Australia 9
DZ - Algeria 9
MX - Messico 8
NG - Nigeria 7
SA - Arabia Saudita 7
TH - Thailandia 7
EG - Egitto 6
HU - Ungheria 6
AL - Albania 5
BA - Bosnia-Erzegovina 5
ID - Indonesia 5
LV - Lettonia 5
TN - Tunisia 5
CI - Costa d'Avorio 4
LT - Lituania 4
NZ - Nuova Zelanda 4
A2 - ???statistics.table.value.countryCode.A2??? 3
BY - Bielorussia 3
GH - Ghana 3
IQ - Iraq 3
MA - Marocco 3
RS - Serbia 3
AR - Argentina 2
EC - Ecuador 2
ET - Etiopia 2
MD - Moldavia 2
PH - Filippine 2
SI - Slovenia 2
SK - Slovacchia (Repubblica Slovacca) 2
UZ - Uzbekistan 2
BD - Bangladesh 1
BW - Botswana 1
CY - Cipro 1
KH - Cambogia 1
KW - Kuwait 1
LB - Libano 1
VE - Venezuela 1
Totale 35.680
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Città #
Ashburn 3.741
Southend 2.629
Seattle 1.771
Fairfield 1.568
Chandler 932
Woodbridge 786
Houston 758
Turin 707
Ann Arbor 630
Cambridge 588
Princeton 583
Wilmington 556
Torino 497
Buffalo 380
Jacksonville 377
Dublin 372
Beijing 358
Berlin 337
San Ramon 282
San Francisco 274
Milan 246
Bern 234
Des Moines 230
Izmir 227
Boardman 224
Chicago 178
Brussels 173
Helsinki 154
Shanghai 151
Council Bluffs 136
San Donato Milanese 131
Zhengzhou 128
Singapore 125
Overland Park 119
Pennsylvania Furnace 119
Saint Petersburg 105
Bologna 104
Zaporozhye 95
Herkenbosch 89
Baltimore 88
San Diego 82
Overberg 81
Norwalk 80
Rome 78
Hong Kong 74
Mountain View 71
Redwood City 70
Vienna 69
Guangzhou 67
Monopoli 66
Galati 64
Hangzhou 64
Las Vegas 63
Menlo Park 63
San Jose 62
Shenzhen 62
Austin 60
Columbus 60
Fremont 51
Amsterdam 47
New York 45
Clearwater 43
Toronto 43
Phoenix 42
Rotterdam 42
Padua 41
University Park 40
Ottawa 39
Redmond 39
Seoul 38
Atlanta 37
Genova 37
Falls Church 36
Muizenberg 34
Frankfurt 33
Sofia 33
Indiana 32
Paris 32
Palermo 31
Lecce 30
San Mateo 30
Malatya 29
Nanjing 29
Ningbo 29
Putian 29
London 28
Dallas 27
Munich 27
Cupertino 25
Dearborn 25
Fuzhou 25
Bremen 23
Islamabad 23
Melun 21
Montréal 21
Florence 20
Piscataway 20
Andover 19
Henderson 19
Washington 19
Totale 23.751
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Nome #
Analysis of HEVC transform throughput requirements for hardware implementations 654
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 510
Design of a Power Conscious, Customizable CDMA Receiver 472
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 456
Comparison between HEVC and Thor based on objective and subjective assessments 432
A Network-on-Chip-based turbo/LDPC decoder architecture 432
A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications 431
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 426
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 426
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 422
Computation reduction for turbo decoding through window skipping 421
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 412
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 407
On optimal and near-optimal turbo decoding using generalized max operator 404
Adaptive Approximated DCT Architectures for HEVC 403
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 402
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 401
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 393
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 391
Multiplierless Mumford and Shah Functional Implementation 385
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 381
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 380
Scalable low-complexity B-spline discretewavelet transform architecture 378
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 377
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 373
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 371
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 365
High speed architectures for finding the firsttwo maximum/minimum values 360
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 350
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 349
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 349
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 348
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 341
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 340
On chip interconnects for multiprocessor turbo decoding architectures 339
Non-recursive max* operator with reduced implementation complexity for turbo decoding 337
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 336
A Flexible UMTS-WiMax Turbo Decoder Architecture 331
Using information centric networking for mobile devices cooperation at the network edge 328
Area Efficient DST Architectures for HEVC 326
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 323
State metric compression techniques for turbo decoder architectures 321
Approximate Arai DCT Architecture for HEVC 317
Improving Network-on-Chip-based Turbo Decoder Architectures 311
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 310
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards 306
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 282
VLSI Architectures for WIMAX Channel Decoders 279
A VLSI architecture for IWT (Integer Wavelet Transform) 273
A new approach to compress the configuration information of programmable devices 262
Mumford and Shah Functional: VLSI Analysis and Implementation 257
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 256
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 254
Implementation of a spread-spectrum-based smart lighting system on an embedded platform 254
Optimization and implementation of the integer wavelet transform for image coding 247
MP-SoC/NoC Architectures for Error Correction 246
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 243
System architecture for error-resilient, embedded JPEG2002 wireless delivery 242
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications 240
Mixed DSP/FPGA implementation of an error-resilient image transmission system based on JPEG2000 239
Design and implementation of a scalable multimedia processor 239
An LDPC Decoder Architecture forWireless Sensor Network Applications 236
FPGA digital down converter IP for SDR terminals 235
High throughput implementation of an adaptive serial concatenation turbo decoder 234
Parametric FPGA early-late DLL implementation for a UMTS receiver 232
FPGA Power Efficient Inverse Lifting Wavelet IP 226
Multimedia SoC: a systolic core for embedded DCT evaluation 221
Reconfigurable DSP IP for Multimedia Applications 221
Flexible blocks for high throughput serially concatenated convolutional codes 214
Multiplierless, Folded 9/7 - 5/3 Wavelet VLSI Architecture 209
A reconfigurable, power-scalable Rake receiver IP for W-CDMA 209
dynDCT: a dynamically adaptable integer DCT 203
FPGA system-on-chip soft IP design: a reconfigurable DSP 200
Reconfigurable coprocessor based JPEG 2000 implementation 197
Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming 196
JPEG2000: Finite Precision Representation and hardware implications 194
Mumford and Shah functional: finite precision analysis and software implementation 192
A flexible encoder architecture for high throughput SeriallyConcatenated Convolutional Codes 188
Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000 188
Real-time implementation of a time-frequency analysis scheme 188
A power-scalable motion estimation coprocessor for energy constrained applications 186
Embedded IWT Evaluation in Reconfigurable Wireless Sensor Network 185
FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories 184
FPGA implementation of a reconfigurable SPIHT coprocessor 183
A statistical model for estimating the effect of process variations on crosstalk noise 180
Error Resilient JPEG2000 Decoding for Wireless Applications 179
dynDCT: a dynamically adaptable integer DCT 178
Folded multiplieriess lifting-based wavelet pipeline 176
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead 173
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations 171
Wireless Sensor Networks a Power Scalable Motion Estimation IP for Hybrid Video Coding 159
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World 159
FPGA Architectures for Fast-Prunable Interleavers 157
Implementation of a SPIHT coprocessor: memory issues and hardware implications 153
DSP implementation of a low complexity motion detection algorithm 153
Error Correcting Arithmetic Coding for JPEG 2000: Memory and Performance Analysis 152
Low-Complexity, Efficient 9/7 Wavelet Filters Implementation 151
Corrections to “Multiplierless, Folded 9/7–5/3 Wavelet VLSI Architecture” 146
JPEG2000 Decoder Architecture for Mobile Applications 144
FPGA superpipelined DSP core for 3G wireless applications 142
Totale 28.734
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Categoria #
all - tutte 88.356
article - articoli 36.895
book - libri 0
conference - conferenze 49.739
curatela - curatele 0
other - altro 0
patent - brevetti 177
selected - selezionate 0
volume - volumi 1.545
Totale 176.712
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20204.647 510 284 213 481 583 493 543 532 501 201 217 89
2020/20213.275 320 400 188 365 234 338 147 252 244 335 247 205
2021/20223.686 178 187 168 259 330 329 347 154 140 267 697 630
2022/20234.146 310 558 178 369 579 542 460 202 341 63 215 329
2023/20241.786 120 149 103 104 165 199 137 160 130 121 195 203
2024/202543 43 0 0 0 0 0 0 0 0 0 0 0
Totale 36.347