PORTO @ Archivio Istituzionale della Ricerca

MARTINA, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 20.583
EU - Europa 16.894
AS - Asia 7.689
SA - Sud America 1.043
AF - Africa 225
OC - Oceania 25
Continente sconosciuto - Info sul continente non disponibili 13
Totale 46.472
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Nazione #
US - Stati Uniti d'America 20.315
IT - Italia 4.557
GB - Regno Unito 3.041
SG - Singapore 2.846
DE - Germania 2.795
FR - Francia 2.567
CN - Cina 2.344
BR - Brasile 855
UA - Ucraina 721
KR - Corea 528
RU - Federazione Russa 484
NL - Olanda 420
IE - Irlanda 413
HK - Hong Kong 361
TR - Turchia 344
VN - Vietnam 342
SE - Svezia 310
CH - Svizzera 301
BE - Belgio 265
FI - Finlandia 244
IN - India 229
AT - Austria 223
CA - Canada 189
ID - Indonesia 158
JP - Giappone 90
RO - Romania 86
ES - Italia 73
ZA - Sudafrica 71
PL - Polonia 70
AR - Argentina 69
PK - Pakistan 66
SN - Senegal 61
MY - Malesia 53
BD - Bangladesh 48
CL - Cile 48
GR - Grecia 48
MX - Messico 47
IR - Iran 43
IL - Israele 42
BG - Bulgaria 40
AP - ???statistics.table.value.countryCode.AP??? 37
JO - Giordania 35
IQ - Iraq 32
TW - Taiwan 28
MA - Marocco 25
EU - Europa 23
CZ - Repubblica Ceca 21
PT - Portogallo 21
AE - Emirati Arabi Uniti 20
EC - Ecuador 20
AU - Australia 17
NO - Norvegia 17
DZ - Algeria 16
CO - Colombia 15
SA - Arabia Saudita 15
EE - Estonia 14
LU - Lussemburgo 14
LT - Lituania 13
DK - Danimarca 12
KE - Kenya 12
HR - Croazia 11
PY - Paraguay 11
AL - Albania 10
EG - Egitto 10
HU - Ungheria 10
TH - Thailandia 10
UZ - Uzbekistan 10
LV - Lettonia 9
TN - Tunisia 9
NG - Nigeria 8
PE - Perù 8
BY - Bielorussia 7
NZ - Nuova Zelanda 7
VE - Venezuela 7
BO - Bolivia 6
BA - Bosnia-Erzegovina 5
DO - Repubblica Dominicana 5
NP - Nepal 5
PH - Filippine 5
AZ - Azerbaigian 4
CI - Costa d'Avorio 4
GH - Ghana 4
HN - Honduras 4
JM - Giamaica 4
KW - Kuwait 4
NI - Nicaragua 4
OM - Oman 4
QA - Qatar 4
TT - Trinidad e Tobago 4
UY - Uruguay 4
A2 - ???statistics.table.value.countryCode.A2??? 3
BN - Brunei Darussalam 3
CR - Costa Rica 3
CY - Cipro 3
LB - Libano 3
MD - Moldavia 3
RS - Serbia 3
SI - Slovenia 3
SK - Slovacchia (Repubblica Slovacca) 3
SV - El Salvador 3
Totale 46.441
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Città #
Ashburn 4.266
Southend 2.629
Seattle 1.777
Fairfield 1.568
Singapore 1.512
Turin 957
Chandler 932
Woodbridge 786
Houston 758
Ann Arbor 630
Cambridge 589
Princeton 583
Beijing 565
Wilmington 556
Torino 497
Santa Clara 494
Buffalo 462
Boardman 448
Dublin 379
Jacksonville 379
Berlin 338
Milan 296
San Francisco 286
Dallas 284
San Ramon 282
Hong Kong 254
Brussels 245
Des Moines 235
Bern 234
Izmir 227
Council Bluffs 215
Chicago 191
Shanghai 181
Seoul 175
Helsinki 167
Jakarta 141
Zhengzhou 137
Ho Chi Minh City 133
San Donato Milanese 131
Los Angeles 129
Overland Park 119
Pennsylvania Furnace 119
Hefei 116
Bologna 114
Saint Petersburg 105
North Bergen 101
Rome 100
Vienna 96
Zaporozhye 95
Herkenbosch 89
Baltimore 88
Guangzhou 88
New York 88
San Diego 82
Overberg 81
Norwalk 80
São Paulo 79
Munich 75
San Jose 72
Columbus 71
Mountain View 71
Redwood City 70
Shenzhen 67
Monopoli 66
Hangzhou 65
Las Vegas 65
Galati 64
Menlo Park 63
Hanoi 62
Amsterdam 60
Austin 60
Lappeenranta 60
Nuremberg 59
Frankfurt am Main 53
Phoenix 52
Fremont 51
Toronto 51
Istanbul 45
Atlanta 44
Clearwater 43
London 43
Rotterdam 42
Padua 41
Ottawa 40
University Park 40
Redmond 39
Genova 37
Paris 37
Falls Church 36
Nanjing 35
Tokyo 35
Muizenberg 34
Frankfurt 33
Sofia 33
Indiana 32
Islamabad 31
Palermo 31
Stockholm 31
Warsaw 31
Lecce 30
Totale 28.788
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Nome #
Analysis of HEVC transform throughput requirements for hardware implementations 781
VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder 545
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware 543
Design of a Power Conscious, Customizable CDMA Receiver 526
Comparison between HEVC and Thor based on objective and subjective assessments 487
A Network-on-Chip-based turbo/LDPC decoder architecture 487
Computation reduction for turbo decoding through window skipping 484
A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications 480
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders 471
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications 464
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor 460
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced 457
An application specific instruction set processor based implementation for signal detection in multiple antenna systems 456
Adaptive Approximated DCT Architectures for HEVC 456
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission 455
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters 455
FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories 454
On optimal and near-optimal turbo decoding using generalized max operator 448
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values 443
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT 440
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures 437
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors 436
VLSI implementation of a multi-mode turbo/LDPC decoder architecture 430
Multiplierless Mumford and Shah Functional Implementation 426
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures 420
Scalable low-complexity B-spline discretewavelet transform architecture 416
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme 413
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding 411
A High Throughput Turbo Decoder VLSI Architecture for 3GPP LTE Standard 405
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures 397
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding 396
High speed architectures for finding the firsttwo maximum/minimum values 396
Non-recursive max* operator with reduced implementation complexity for turbo decoding 392
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation 391
Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation 389
Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding 389
State metric compression techniques for turbo decoder architectures 383
On chip interconnects for multiprocessor turbo decoding architectures 376
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding 375
Approximate Arai DCT Architecture for HEVC 372
Area Efficient DST Architectures for HEVC 370
A Flexible UMTS-WiMax Turbo Decoder Architecture 370
Improving Network-on-Chip-based Turbo Decoder Architectures 358
Using information centric networking for mobile devices cooperation at the network edge 352
Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation 344
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards 344
Odd type DCT/DST for video coding: Relationships and low-complexity implementations 329
VLSI Architectures for WIMAX Channel Decoders 316
A new approach to compress the configuration information of programmable devices 303
Implementation of a spread-spectrum-based smart lighting system on an embedded platform 300
A VLSI architecture for IWT (Integer Wavelet Transform) 300
Optimization and implementation of the integer wavelet transform for image coding 299
Mumford and Shah Functional: VLSI Analysis and Implementation 297
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding 294
Turbo decoder VLSI architecture with non-recursive max* operator for 3GPP LTE standard 289
MP-SoC/NoC Architectures for Error Correction 289
Design and implementation of a scalable multimedia processor 288
FPGA implementation of time-frequency analysis algorithms for laser welding monitoring 286
An LDPC Decoder Architecture forWireless Sensor Network Applications 286
FPGA digital down converter IP for SDR terminals 276
High throughput implementation of an adaptive serial concatenation turbo decoder 271
System architecture for error-resilient, embedded JPEG2002 wireless delivery 266
Parametric FPGA early-late DLL implementation for a UMTS receiver 263
VLSI Reed-Solomon Decoder Architecture for Networked Multimedia Applications 259
Mixed DSP/FPGA implementation of an error-resilient image transmission system based on JPEG2000 258
Multiplierless, Folded 9/7 - 5/3 Wavelet VLSI Architecture 255
dynDCT: a dynamically adaptable integer DCT 252
A reconfigurable, power-scalable Rake receiver IP for W-CDMA 252
FPGA Power Efficient Inverse Lifting Wavelet IP 250
Reconfigurable DSP IP for Multimedia Applications 250
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead 244
Multimedia SoC: a systolic core for embedded DCT evaluation 242
A power-scalable motion estimation coprocessor for energy constrained applications 235
Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000 234
Mumford and Shah functional: finite precision analysis and software implementation 234
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World 230
Flexible blocks for high throughput serially concatenated convolutional codes 229
FPGA implementation of a reconfigurable SPIHT coprocessor 229
Real-time implementation of a time-frequency analysis scheme 229
FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories 228
FPGA system-on-chip soft IP design: a reconfigurable DSP 226
Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming 226
JPEG2000: Finite Precision Representation and hardware implications 223
Reconfigurable coprocessor based JPEG 2000 implementation 223
An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks 218
Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle 215
dynDCT: a dynamically adaptable integer DCT 211
Tutorial: A Versatile Bio-Inspired System for Processing and Transmission of Muscular Information 211
A flexible encoder architecture for high throughput SeriallyConcatenated Convolutional Codes 209
A statistical model for estimating the effect of process variations on crosstalk noise 207
Motion Analysis for Experimental Evaluation of an Event-Driven FES System 206
Error Resilient JPEG2000 Decoding for Wireless Applications 201
FPGA Architectures for Fast-Prunable Interleavers 200
Embedded IWT Evaluation in Reconfigurable Wireless Sensor Network 199
Live Demonstration: Event-Driven Hand Gesture Recognition for Wearable Human-Machine Interface 199
DSP implementation of a low complexity motion detection algorithm 195
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations 194
Wireless Sensor Networks a Power Scalable Motion Estimation IP for Hybrid Video Coding 193
Folded multiplieriess lifting-based wavelet pipeline 192
Error Correcting Arithmetic Coding for JPEG 2000: Memory and Performance Analysis 192
Totale 33.182
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Categoria #
all - tutte 127.659
article - articoli 52.326
book - libri 0
conference - conferenze 72.634
curatela - curatele 0
other - altro 0
patent - brevetti 300
selected - selezionate 0
volume - volumi 2.399
Totale 255.318
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.768 0 0 0 0 0 338 147 252 244 335 247 205
2021/20223.686 178 187 168 259 330 329 347 154 140 267 697 630
2022/20234.146 310 558 178 369 579 542 460 202 341 63 215 329
2023/20241.786 120 149 103 104 165 199 137 160 130 121 195 203
2024/20255.257 148 669 302 565 445 378 318 352 714 349 434 583
2025/20265.688 1.009 882 963 1.274 1.032 528 0 0 0 0 0 0
Totale 47.249