| Nome |
# |
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Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation, file e384c42d-f6cd-d4b2-e053-9f05fe0a1d67
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1.239
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Multiplierless, Folded 9/7 - 5/3 Wavelet VLSI Architecture, file e384c42e-0281-d4b2-e053-9f05fe0a1d67
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1.117
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|
A Flexible UMTS-WiMax Turbo Decoder Architecture, file e384c42e-0756-d4b2-e053-9f05fe0a1d67
|
971
|
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Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding, file e384c42e-0ac7-d4b2-e053-9f05fe0a1d67
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966
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|
On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders, file e384c42e-179b-d4b2-e053-9f05fe0a1d67
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908
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VLSI implementation of a multi-mode turbo/LDPC decoder architecture, file e384c42e-269b-d4b2-e053-9f05fe0a1d67
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838
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State metric compression techniques for turbo decoder architectures, file e384c42e-187c-d4b2-e053-9f05fe0a1d67
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819
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High speed architectures for finding the firsttwo maximum/minimum values, file e384c42e-1d94-d4b2-e053-9f05fe0a1d67
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817
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On chip interconnects for multiprocessor turbo decoding architectures, file e384c42e-18d8-d4b2-e053-9f05fe0a1d67
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794
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Hardware Design of a Low Complexity, Parallel Interleaver for WiMax Duo-Binary Turbo Decoding, file e384c42e-0759-d4b2-e053-9f05fe0a1d67
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764
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A Network-on-Chip-based turbo/LDPC decoder architecture, file e384c42e-1edc-d4b2-e053-9f05fe0a1d67
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734
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Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures, file e384c42e-307f-d4b2-e053-9f05fe0a1d67
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723
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VLSI Implementation of WiMax Convolutional Turbo Code Encoder and Decoder, file e384c42e-08d6-d4b2-e053-9f05fe0a1d67
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722
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Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation using Graphics Processing Unit and Dedicated Hardware, file e384c42e-39d3-d4b2-e053-9f05fe0a1d67
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556
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Multiplierless Mumford and Shah Functional Implementation, file e384c42e-0ad2-d4b2-e053-9f05fe0a1d67
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531
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FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories, file e384c42f-3209-d4b2-e053-9f05fe0a1d67
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512
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Mumford and Shah Functional: VLSI Analysis and Implementation, file e384c42d-f6cb-d4b2-e053-9f05fe0a1d67
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479
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A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values, file e384c42e-38d4-d4b2-e053-9f05fe0a1d67
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475
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VLSI Implementation of a Non-Binary Decoder
Based on the Analog Digital Belief Propagation, file e384c42e-2792-d4b2-e053-9f05fe0a1d67
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473
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Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications, file e384c42e-35bd-d4b2-e053-9f05fe0a1d67
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457
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On optimal and near-optimal turbo decoding using generalized max operator, file e384c42e-02d0-d4b2-e053-9f05fe0a1d67
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444
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Comparison between HEVC and Thor based on objective and subjective assessments, file e384c42f-00c8-d4b2-e053-9f05fe0a1d67
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437
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Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced, file e384c42e-3044-d4b2-e053-9f05fe0a1d67
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436
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Computation reduction for turbo decoding through window skipping, file e384c42e-a896-d4b2-e053-9f05fe0a1d67
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433
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Adaptive Approximated DCT Architectures for HEVC, file e384c42f-312c-d4b2-e053-9f05fe0a1d67
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422
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Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT, file e384c42d-cfdd-d4b2-e053-9f05fe0a1d67
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372
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Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures, file e384c42e-3ca5-d4b2-e053-9f05fe0a1d67
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336
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An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission, file e384c42e-3b60-d4b2-e053-9f05fe0a1d67
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325
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Implementation of a spread-spectrum-based smart lighting system on an embedded platform, file e384c42e-8c93-d4b2-e053-9f05fe0a1d67
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317
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Area Efficient DST Architectures for HEVC, file e384c42f-96fc-d4b2-e053-9f05fe0a1d67
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317
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Approximate Arai DCT Architecture for HEVC, file e384c42f-ce7d-d4b2-e053-9f05fe0a1d67
|
314
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VLSI Architectures for WIMAX Channel Decoders, file e384c42e-036e-d4b2-e053-9f05fe0a1d67
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307
|
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Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures, file e384c42e-17f2-d4b2-e053-9f05fe0a1d67
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307
|
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Non-recursive max* operator with reduced implementation complexity for turbo decoding, file e384c42e-1c94-d4b2-e053-9f05fe0a1d67
|
307
|
|
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards, file e384c42e-1a76-d4b2-e053-9f05fe0a1d67
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291
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High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters, file e384c42f-990c-d4b2-e053-9f05fe0a1d67
|
252
|
|
Using information centric networking for mobile devices cooperation at the network edge, file e384c42e-7e04-d4b2-e053-9f05fe0a1d67
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249
|
|
Improving Network-on-Chip-based Turbo Decoder Architectures, file e384c42e-288c-d4b2-e053-9f05fe0a1d67
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242
|
|
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors, file e384c42e-3be5-d4b2-e053-9f05fe0a1d67
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229
|
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An application specific instruction set processor based implementation for signal detection in multiple antenna systems, file e384c42e-1561-d4b2-e053-9f05fe0a1d67
|
214
|
|
An LDPC Decoder Architecture forWireless Sensor Network Applications, file e384c42e-18bf-d4b2-e053-9f05fe0a1d67
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191
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Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation, file e384c42e-1bed-d4b2-e053-9f05fe0a1d67
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145
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Scalable low-complexity B-spline discretewavelet transform architecture, file e384c42e-0416-d4b2-e053-9f05fe0a1d67
|
137
|
|
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding, file e384c42e-8766-d4b2-e053-9f05fe0a1d67
|
125
|
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Odd type DCT/DST for video coding: Relationships and low-complexity implementations, file e384c42f-dd63-d4b2-e053-9f05fe0a1d67
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119
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A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography, file e384c432-880b-d4b2-e053-9f05fe0a1d67
|
102
|
|
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World, file e384c431-16fe-d4b2-e053-9f05fe0a1d67
|
66
|
|
Advanced Data Chain Technologies for the Next Generation of Earth Observation Satellites Supporting On-Board Processing for Rapid Civil Alerts, file e384c434-1b3b-d4b2-e053-9f05fe0a1d67
|
63
|
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Assessing the feasibility of augmenting fall detection systems by relying on UWB-based position tracking and a home robot, file e384c432-5173-d4b2-e053-9f05fe0a1d67
|
61
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A low power architecture for AER event-processing microcontroller, file e384c430-0d68-d4b2-e053-9f05fe0a1d67
|
54
|
|
An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks, file e384c432-8140-d4b2-e053-9f05fe0a1d67
|
52
|
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Approximate-Computing Architectures for Motion Estimation in HEVC, file e384c430-b7d5-d4b2-e053-9f05fe0a1d67
|
51
|
|
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead, file e384c432-c54b-d4b2-e053-9f05fe0a1d67
|
50
|
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Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle, file e384c433-afba-d4b2-e053-9f05fe0a1d67
|
50
|
|
HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology, file e384c434-0cde-d4b2-e053-9f05fe0a1d67
|
49
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An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding, file e384c431-67ea-d4b2-e053-9f05fe0a1d67
|
46
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Live Demonstration: Tactile Events from Off-The-Shelf Sensors in a Robotic Skin, file e384c430-3c5a-d4b2-e053-9f05fe0a1d67
|
44
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Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World, file e384c430-e597-d4b2-e053-9f05fe0a1d67
|
44
|
|
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis, file e384c431-94bf-d4b2-e053-9f05fe0a1d67
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44
|
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Motion Analysis for Experimental Evaluation of an Event-Driven FES System, file e384c434-3d98-d4b2-e053-9f05fe0a1d67
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44
|
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NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks, file e384c432-913a-d4b2-e053-9f05fe0a1d67
|
43
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A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things, file e384c433-b17c-d4b2-e053-9f05fe0a1d67
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42
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Efficient hardware implementation of the LEDAcrypt Decoder, file e384c433-989b-d4b2-e053-9f05fe0a1d67
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41
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VLSI architectures of a wiener filter for video coding, file e384c433-f35c-d4b2-e053-9f05fe0a1d67
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41
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Tutorial: A Versatile Bio-Inspired System for Processing and Transmission of Muscular Information, file e384c434-3103-d4b2-e053-9f05fe0a1d67
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41
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Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks, file e384c432-4159-d4b2-e053-9f05fe0a1d67
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38
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|
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms, file e384c434-92d5-d4b2-e053-9f05fe0a1d67
|
38
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Analysis of HEVC transform throughput requirements for hardware implementations, file e384c42f-874b-d4b2-e053-9f05fe0a1d67
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36
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A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress, file e384c432-d7cf-d4b2-e053-9f05fe0a1d67
|
34
|
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Very Low Latency Architecture for Earth Observation Satellite Onboard Data Handling, Compression, and Encryption, file e384c434-0bf7-d4b2-e053-9f05fe0a1d67
|
34
|
|
VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT), file e384c432-55de-d4b2-e053-9f05fe0a1d67
|
33
|
|
FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks, file e384c432-3cde-d4b2-e053-9f05fe0a1d67
|
31
|
|
Live Demonstration: Event-Driven Hand Gesture Recognition for Wearable Human-Machine Interface, file e384c434-3aad-d4b2-e053-9f05fe0a1d67
|
30
|
|
Smart portable pen for continuous monitoring of anaesthetics in human serum with machine learning, file e384c433-e315-d4b2-e053-9f05fe0a1d67
|
29
|
|
An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding, file e384c431-00ce-d4b2-e053-9f05fe0a1d67
|
27
|
|
Towards Optimal Green Plant Irrigation: Watering and Body Electrical Impedance, file e384c432-ae49-d4b2-e053-9f05fe0a1d67
|
26
|
|
EO-ALERT: A Novel Architecture for the Next Generation of Earth Observation Satellites Supporting Rapid Civil Alerts, file e384c434-1a17-d4b2-e053-9f05fe0a1d67
|
26
|
|
Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network, file e384c432-7e6d-d4b2-e053-9f05fe0a1d67
|
24
|
|
Integrated Light Sensing and Communication for LED Lighting, file e384c430-5b9f-d4b2-e053-9f05fe0a1d67
|
22
|
|
A Novel Satellite Architecture for the Next Generation of Earth Observation Satellites Supporting Rapid Alerts, file e384c434-46bf-d4b2-e053-9f05fe0a1d67
|
22
|
|
Guest EditorialSpecial Issue on Selected Papers from IEEE BioCAS 2017, file e384c430-8655-d4b2-e053-9f05fe0a1d67
|
21
|
|
Real-time implementation of fast discriminative scale space tracking algorithm, file e384c433-b17e-d4b2-e053-9f05fe0a1d67
|
21
|
|
LOW LATENCY ON-BOARD DATA HANDLING FOR EARTH OBSERVATION SATELLITES USING OFF-THE-SHELF COMPONENTS, file e384c434-0348-d4b2-e053-9f05fe0a1d67
|
21
|
|
Low Latency Protocols Investigation for Event-Driven Wireless Body Area Networks, file e384c434-2eaa-d4b2-e053-9f05fe0a1d67
|
20
|
|
vrLab: A Virtual and Remote Low Cost Electronics Lab Platform, file e384c434-5d3c-d4b2-e053-9f05fe0a1d67
|
20
|
|
PruNet: Class-Blind Pruning Method For Deep Neural Networks, file e384c430-4db4-d4b2-e053-9f05fe0a1d67
|
19
|
|
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding, file e384c42e-8c94-d4b2-e053-9f05fe0a1d67
|
18
|
|
A Novel Framework for Designing Directional Linear Transforms with Application to Video Compression, file e384c430-dbea-d4b2-e053-9f05fe0a1d67
|
17
|
|
Advanced Data Chain Technologies for the Next Generation of Earth Observation Satellites Supporting On-Board Processing for Rapid Civil Alerts, file e384c432-baa2-d4b2-e053-9f05fe0a1d67
|
16
|
|
CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor, file e384c434-23f9-d4b2-e053-9f05fe0a1d67
|
16
|
|
A Low Cost ALS and VLC Circuit for Solid State Lighting, file e384c431-00cf-d4b2-e053-9f05fe0a1d67
|
15
|
|
High-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator, file e384c434-3e2b-d4b2-e053-9f05fe0a1d67
|
15
|
|
R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors, file e384c434-16cf-d4b2-e053-9f05fe0a1d67
|
13
|
|
A Low Cost ALS and VLC Circuit for Solid State Lighting, file e384c430-f414-d4b2-e053-9f05fe0a1d67
|
12
|
|
An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor, file e384c432-7e92-d4b2-e053-9f05fe0a1d67
|
12
|
|
NACU: A Non-Linear Arithmetic Unit for Neural Networks, file e384c432-84a4-d4b2-e053-9f05fe0a1d67
|
12
|
|
Impulse-based asynchronous serial communication protocol on optical fiber link for AER systems, file e384c432-b660-d4b2-e053-9f05fe0a1d67
|
11
|
|
Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs, file e384c434-a64a-d4b2-e053-9f05fe0a1d67
|
11
|
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Low-Complexity Reconfigurable DCT-V Architecture, file e384c432-ccba-d4b2-e053-9f05fe0a1d67
|
10
|
|
DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks, file e384c434-3a1e-d4b2-e053-9f05fe0a1d67
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10
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| Totale |
23.951 |
Archivio Istituzionale della Ricerca