DELIGIANNIS, NIKOLAOS

DELIGIANNIS, NIKOLAOS  

Dipartimento di Automatica e Informatica  

060034  

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Risultati 1 - 15 di 15 (tempo di esecuzione: 0.036 secondi).
Citazione Data di pubblicazione Autori File
Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults / Deligiannis, N., Cantoro, R., SONZA REORDA, M., Habib, S.E.D.. - (2024), pp. 124-129. (International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Kielce (POL) 03-05 April 2024) [10.1109/DDECS60919.2024.10508899]. 1-gen-2024 Deligiannis, NikolaosCantoro, RiccardoSonza Reorda Matteo + DDECS2024__Evaluating_the_Reliability_of_Integer_Multipliers_With_Respect_to_Permanent_Faults.pdfEvaluating_the_Reliability_of_Integer_Multipliers_With_Respect_to_Permanent_Faults.pdf
Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects / Bartolomucci, M., Deligiannis, N., Cantoro, R., Sonza Reorda, M.. - (2024). (International Symposium on On-Line Testing and Robust System Design (IOLTS) Rennes (FRA) 03-05 July 2024) [10.1109/IOLTS60994.2024.10616077]. 1-gen-2024 Bartolomucci, MichelangeloDeligiannis, NikolaosCantoro, RiccardoSonza Reorda, Matteo IOLTS-24_CameraReady.pdfFault_Grading_Techniques_for_Evaluating_Software-Based_Self-Test_with_Respect_to_Small_Delay_Defects.pdf
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors / Anders, J., Andreu, P., Becker, B., Becker, S., Cantoro, R., Deligiannis, N., Elhamawy, N., Faller, T., Hernandez, C., Mentens, N., Namazi Rizi, M., Polian, I., Sajadi, A., Sauer, M., Schwachhofer, D., SONZA REORDA, M., Stefanov, T., Tuzov, I., Wagner, S., Zidaric, N.. - (2023), pp. 1-10. (2023 IEEE European Test Symposium (ETS) Venice (Italy) 22-26 May 2023) [10.1109/ETS56758.2023.10174099]. 1-gen-2023 Riccardo CantoroNikolaos DeligiannisMatteo Sonza Reorda + ETS_RISC_V_testing_safety_security.pdfA_Survey_of_Recent_Developments_in_Testability_Safety_and_Security_of_RISC-V_Processors.pdf
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors / Deligiannis, N., Faller, T., Iacopo, G., Cantoro, R., Becker, B., SONZA REORDA, M.. - (2023), pp. 1-6. (Asian Test Symposium (ATS) Beijing (China) 14-17 October 2023) [10.1109/ATS59501.2023.10317988]. 1-gen-2023 Nikolaos DeligiannisRiccardo CantoroMatteo Sonza Reorda + _ATS2023__Automatic_Identification_of_Functionally_Untestable_Cell_Aware_Faults_in_Microprocessors.pdfAutomatic_Identification_of_Functionally_Untestable_Cell-Aware_Faults_in_Microprocessors.pdf
Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing / Deligiannis, N., Faller, T., Chenghan, Z., Cantoro, R., Becker, B., SONZA REORDA, M.. - (2023), pp. 1-5. (2023 IEEE European Test Symposium (ETS) Venice (Italy) 22-26 May 2023) [10.1109/ETS56758.2023.10174232]. 1-gen-2023 Nikolaos DeligiannisRiccardo CantoroMatteo Sonza Reorda + _ETS2023__Automating_the_Generation_of_Functional_Stress_Inducing_Stimuli_for_Burn_In_Testing.pdfAutomating_the_Generation_of_Functional_Stress_Inducing_Stimuli_for_Burn-In_Testing.pdf
Constraint-Based Automatic SBST Generation for RISC-V Processor Families / Faller, T., Deligiannis, N., Schwörer, M., SONZA REORDA, M., Becker, B.. - (2023), pp. 1-6. (2023 IEEE European Test Symposium (ETS) Venice (Italy) 22-26 May 2023) [10.1109/ETS56758.2023.10174156]. 1-gen-2023 Nikolaos DeligiannisMatteo Sonza Reorda + _ETS2023__Constraint_Based_Automatic_SBST_Generation_for_RISC_V_Processor_Families.pdfConstraint-Based_Automatic_SBST_Generation_for_RISC-V_Processor_Families.pdf
Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters / Rodriguez, E., Deligiannis, N., Sini, J., Cantoro, R., SONZA REORDA, M.. - 13999:(2023), pp. 444-457. (ISC High Performance 2023 International Workshops Hamburg (DEU) May 21–25, 2023) [10.1007/978-3-031-40843-4_33]. 1-gen-2023 Esteban RodriguezNikolaos DeligiannisJacopo SiniRiccardo CantoroMatteo Sonza Reorda _RV_HPC2023__FULL_FORMAT__Functional_Testing_with_SLTs__A_step_towards_reliable_RISC_V_Based_HPC_commodity_clusters.pdf978-3-031-40843-4_33.pdf
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms / Deligiannis, N., Cantoro, R., SONZA REORDA, M., Traiola, M., Valea, E.. - (2022), pp. 23-24. (Dependable Systems and Networks 27-30 June 2022) [10.1109/DSN-S54099.2022.00017]. 1-gen-2022 Nikolaos DeligiannisRiccardo CantoroMatteo Sonza ReordaEmanuele Valea + DSN_2022.pdfImproving_the_Fault_Resilience_of_Neural_Network_Applications_Through_Security_Mechanisms.pdf
New Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity of Complex SoCs / Deligiannis, N.. - (2022). (European Test Symposium (ETS) ). 1-gen-2022 Nikolaos Deligiannis ETS2022_PhD_Forum.pdf
Using Formal Methods to Support the Development of STLs for GPUs / Deligiannis, N., Faller, T., RODRIGUEZ CONDIA, J.E., Cantoro, R., Becker, B., SONZA REORDA, M.. - (2022), pp. 84-89. (Asian Test Symposium (ATS) Taiwan 21-24 November 2022) [10.1109/ATS56056.2022.00027]. 1-gen-2022 Nikolaos DeligiannisJosie Esteban RodriguezRiccardo CantoroMatteo Sonza Reorda + _ATS2022__Using_Formal_Methods_to_Support_the_Development_of_STLs_for_GPUs.pdfUsing_Formal_Methods_to_Support_the_Development_of_STLs_for_GPUs.pdf
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor / Deligiannis, N., Cantoro, R., Faller, T., Paxian, T., Becker, B., SONZA REORDA, M.. - (2021), pp. 73-78. (Asian Test Symposium (ATS) 22-25 Nov. 2021) [10.1109/ATS52891.2021.00025]. 1-gen-2021 Nikolaos DeligiannisRiccardo CantoroMatteo Sonza Reorda + 2021178103.pdfEffective_SAT-based_Solutions_for_Generating_Functional_Sequences_Maximizing_the_Sustained_Switching_Activity_in_a_Pipelined_Processor.pdf
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques / Deligiannis, N., Cantoro, R., Sonza Reorda, M.. - (2021), pp. 535-540. (Digital System Design (DSD) 01-03 September 2021) [10.1109/DSD53832.2021.00086]. 1-gen-2021 Deligiannis, NikolaosCantoro, RiccardoSonza Reorda, Matteo _DSD2021__Maximizing_the_Switching_Activity_of_a_Processor_via_Evolutionary_Tecnhiques.pdfMaximizing_the_Switching_Activity_of_Different_Modules_Within_a_Processor_Core_via_Evolutionary_Techniques.pdf
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core / Deligiannis, N., Cantoro, R., Sauer, M., Becker, B., Reorda, M.S.. - (2021), pp. 1-7. (2021 IEEE 39th VLSI Test Symposium (VTS) 25-28 April 2021) [10.1109/VTS50974.2021.9441040]. 1-gen-2021 Deligiannis, NikolaosCantoro, RiccardoReorda, Matteo Sonza + 09441040.pdf
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network / Cantoro, R., Deligiannis, N., Reorda, M.S., Traiola, M., Valea, E.. - ELETTRONICO. - (2020), pp. 1-4. (2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ) [10.1109/DFT50435.2020.9250869]. 1-gen-2020 Cantoro, RiccardoDeligiannis, NikolaosReorda, Matteo SonzaValea, Emanuele + Camera Ready.pdf09250869.pdf
Evaluating the Code Encryption Effects on Memory Fault Resilience / Cantoro, R., Deligiannis, N., Sonza Reorda, M., Traiola, M., Valea, E.. - ELETTRONICO. - (2020), pp. 1-6. (21st IEEE Latin-American Test Symposium, LATS 2020 Maceio, Brazil 30 March-2 April 2020) [10.1109/LATS49555.2020.9093670]. 1-gen-2020 Cantoro R.Deligiannis N.Sonza Reorda M.Valea E. + PUBLISHED-09093670.pdf_LATS2020__Evaluating_the_Code_Encryption_Effects_on_Memory_Fault_Resilience.pdf