In several test and reliability problems (from test generation to FMECA and Burn In) it is important to preliminarily identify those lines in a circuit netlist, which can not be controlled, i.e., can not be toggled to both logic values no matter the applied stimuli. Several techniques have been proposed in the past to attack this problem. In this paper we consider the case where the circuit is a pipelined processor, discuss the specific challenges of this scenario and propose some techniques to automatically identify some of the uncontrollable lines. The approach we devised uses SAT solving as underlying technology. We report the results we gathered on the OR1200 processor, showing that our method allows to trade off between the required computational effort and the achieved results. When compared with results produced by a commercial tool, our approach is able to identify a much higher number of uncontrollable lines with reasonable computational requirements.
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core / Deligiannis, Nikolaos; Cantoro, Riccardo; Sauer, Matthias; Becker, Bernd; Reorda, Matteo Sonza. - (2021), pp. 1-7. (Intervento presentato al convegno 2021 IEEE 39th VLSI Test Symposium (VTS) nel 25-28 April 2021) [10.1109/VTS50974.2021.9441040].
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core
Deligiannis, Nikolaos;Cantoro, Riccardo;Reorda, Matteo Sonza
2021
Abstract
In several test and reliability problems (from test generation to FMECA and Burn In) it is important to preliminarily identify those lines in a circuit netlist, which can not be controlled, i.e., can not be toggled to both logic values no matter the applied stimuli. Several techniques have been proposed in the past to attack this problem. In this paper we consider the case where the circuit is a pipelined processor, discuss the specific challenges of this scenario and propose some techniques to automatically identify some of the uncontrollable lines. The approach we devised uses SAT solving as underlying technology. We report the results we gathered on the OR1200 processor, showing that our method allows to trade off between the required computational effort and the achieved results. When compared with results produced by a commercial tool, our approach is able to identify a much higher number of uncontrollable lines with reasonable computational requirements.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2906818