statistiche ricercatore

Nazione	#
US - Stati Uniti d'America	653
SG - Singapore	271
VN - Vietnam	215
IT - Italia	193
CN - Cina	150
RU - Federazione Russa	102
DE - Germania	96
GB - Regno Unito	85
HK - Hong Kong	60
KR - Corea	48
NL - Olanda	48
FR - Francia	36
BR - Brasile	34
IN - India	23
BE - Belgio	22
FI - Finlandia	21
IE - Irlanda	19
IL - Israele	19
JP - Giappone	19
TR - Turchia	12
TH - Thailandia	11
TW - Taiwan	11
ID - Indonesia	10
MX - Messico	9
PH - Filippine	9
PK - Pakistan	8
AT - Austria	7
CA - Canada	7
IQ - Iraq	7
IR - Iran	6
JO - Giordania	6
UA - Ucraina	6
AR - Argentina	5
CH - Svizzera	5
PL - Polonia	5
EC - Ecuador	4
KE - Kenya	3
EE - Estonia	2
ES - Italia	2
GR - Grecia	2
RO - Romania	2
SE - Svezia	2
UZ - Uzbekistan	2
AL - Albania	1
AZ - Azerbaigian	1
BA - Bosnia-Erzegovina	1
BD - Bangladesh	1
BY - Bielorussia	1
CL - Cile	1
CO - Colombia	1
DK - Danimarca	1
ET - Etiopia	1
HR - Croazia	1
KG - Kirghizistan	1
KH - Cambogia	1
KZ - Kazakistan	1
LU - Lussemburgo	1
MY - Malesia	1
NO - Norvegia	1
PA - Panama	1
PT - Portogallo	1
RS - Serbia	1
SA - Arabia Saudita	1
SN - Senegal	1
TN - Tunisia	1
VG - Isole Vergini Britanniche	1
ZA - Sudafrica	1
Totale	2.281

Nome	#
An efficient method for the test of embedded memory cores during the operational phase	444
Device-Aware Test for Anomalous Charge Trapping in FeFETs	277
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks	208
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs	199
Recent Trends and Perspectives on Defect-Oriented Testing	196
Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips	194
Using STLs for Effective In-field Test of GPUs	174
Defects, Fault Modeling, and Test Development Framework for FeFETs	172
A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers	158
Untestable faults identification in GPGPUs for safety-critical applications	145
Device-Aware Test for Threshold Voltage Shifting in FeFET	143
A Data-Driven ANN-Based Model for FeCAP & FeFET: Orienting to SPICE and Circuit Design	5
Totale	2.315

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2020/2021	7	0	0	0	0	0	0	0	0	0	0	5	2
2021/2022	94	3	4	2	4	4	4	1	5	1	35	7	24
2022/2023	229	17	31	19	25	31	27	17	13	27	5	7	10
2023/2024	68	6	9	3	7	8	5	6	6	3	6	4	5
2024/2025	550	4	31	35	95	56	55	42	48	70	16	32	66
2025/2026	1.041	45	39	35	90	59	63	214	101	241	135	19	0
Totale													2.315

PORTO @ Archivio Istituzionale della Ricerca