The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Device-aware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.

Device-Aware Test for Anomalous Charge Trapping in FeFETs / Yuan, Sicong; Wang, Changhao; Fieback, Moritz; Xun, Hanzhi; Taouil, Mottaqiallah; Li, Xiuyan; Wang, Lin; Chen, Danyang; Bellarmino, Nicolò; Cantoro, Riccardo; Hamdioui, Said. - (2025), pp. 635-641. (Intervento presentato al convegno 30th Asia and South Pacific Design Automation Conference ASP-DAC 2025 tenutosi a Tokyo (JPN) nel Jan. 20-23, 2025) [10.1145/3658617.3697755].

Device-Aware Test for Anomalous Charge Trapping in FeFETs

Nicolò Bellarmino;Riccardo Cantoro;Said Hamdioui
2025

Abstract

The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Device-aware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.
2025
979-8-4007-0635-6
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2992732