Automotive System-on-Chip (SoC) performances have enormously increased in the last decade. Therefore, bare-metal safety-critical applications have shifted to the new application paradigm written at the Operating System layer, i.e., on top of Real-Time Operating Systems (RTOS). The RTOS stores needed data and instructions in the embedded memories. Therefore, potential corruption in these memories could generate non-deterministic, wrong behaviors. Online software or hardware testing mechanisms detect and sometimes correct such dangerous situations. In either case, the application programmer has to devise special tasks devoted to testing and must ensure fully working synchronization mechanisms without impacting the feasibility of the RTOS scheduler. This paper investigates the impact on the scheduling and reliability of an RTOS when hardware and software memory BIST periodically test embedded RAMs in the field. The results are obtained on a real automotive SoC belonging to the SPC58 family from ST Microelectronics.

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level / Angione, Francesco; Bernardi, Paolo; Filipponi, Gabriele; Tempesta, Claudia; SONZA REORDA, Matteo; Appello, Davide; Ugioli, Roberto; Tancorre, Vincenzo. - (2022). ((Intervento presentato al convegno International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems tenutosi a Austin (USA) nel 19-21 October 2022 [10.1109/DFT56152.2022.9962338].

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level

Francesco Angione;Paolo Bernardi;Gabriele Filipponi;Claudia Tempesta;Matteo Sonza Reorda;
2022

Abstract

Automotive System-on-Chip (SoC) performances have enormously increased in the last decade. Therefore, bare-metal safety-critical applications have shifted to the new application paradigm written at the Operating System layer, i.e., on top of Real-Time Operating Systems (RTOS). The RTOS stores needed data and instructions in the embedded memories. Therefore, potential corruption in these memories could generate non-deterministic, wrong behaviors. Online software or hardware testing mechanisms detect and sometimes correct such dangerous situations. In either case, the application programmer has to devise special tasks devoted to testing and must ensure fully working synchronization mechanisms without impacting the feasibility of the RTOS scheduler. This paper investigates the impact on the scheduling and reliability of an RTOS when hardware and software memory BIST periodically test embedded RAMs in the field. The results are obtained on a real automotive SoC belonging to the SPC58 family from ST Microelectronics.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2971008