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Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience
In corso di stampa Desogus, Marco; Sterpone, Luca; Sabena, Davide; Ullah, Anees; Mario, Porrmann; Jens, Hagemeyer; Jorgan, Ilstad
Real-Time SEU Tolerant Circuits on SRAM-based FPGAs
In corso di stampa Sterpone, Luca; Ullah, Anees
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs
2014 SANCHEZ SANCHEZ, EDGAR ERNESTO; Sterpone, Luca; Ullah, Anees
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems
2013 SONZA REORDA, Matteo; Sterpone, Luca; Ullah, Anees
Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture
2013 Sterpone, Luca; Sabena, Davide; Ullah, Anees; Porrmann, M.; Hagemeyer, J.; Ilstad, J.
On the Optimal Reconfiguration Times for TMR Circuits on SRAM based FPGAs
2013 Sterpone, Luca; Ullah, Anees
Phase compensated differential based quadrature direct digital frequency synthesis
2012 Ullah, Anees; Hazrat, Ali; Yasir Ali, Khan; Muhammad, Aamir; Nazim, Ali; K. M., Yahya
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience / Desogus, Marco; Sterpone, Luca; Sabena, Davide; Ullah, Anees; Mario, Porrmann; Jens, Hagemeyer; Jorgan, Ilstad. - (In corso di stampa). (Intervento presentato al convegno Radiation Effects on Components and Systems 2013). | In corso di stampa | DESOGUS, MARCOSTERPONE, LucaSABENA, DAVIDEULLAH, ANEES + | - |
| Real-Time SEU Tolerant Circuits on SRAM-based FPGAs / Sterpone, Luca; Ullah, Anees. - (In corso di stampa). (Intervento presentato al convegno Radiation Effects on Components and Systems 2013 tenutosi a Oxford nel 23rd-27th September, 2013). | In corso di stampa | STERPONE, LucaULLAH, ANEES | - |
| Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs / SANCHEZ SANCHEZ, EDGAR ERNESTO; Sterpone, Luca; Ullah, Anees. - (2014), pp. 1-6. (Intervento presentato al convegno 24th International Conference on Field Programmable Logic and Applications (FPL), 2014) [10.1109/FPL.2014.6927478]. | 1-gen-2014 | SANCHEZ SANCHEZ, EDGAR ERNESTOSTERPONE, LucaULLAH, ANEES | - |
| An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems / SONZA REORDA, Matteo; Sterpone, Luca; Ullah, Anees. - ELETTRONICO. - (2013), pp. 149-155. (Intervento presentato al convegno IEEE European Test Symposium). | 1-gen-2013 | SONZA REORDA, MatteoSTERPONE, LucaULLAH, ANEES | - |
| Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture / Sterpone, Luca; Sabena, Davide; Ullah, Anees; Porrmann, M.; Hagemeyer, J.; Ilstad, J.. - ELETTRONICO. - (2013), pp. 184-188. (Intervento presentato al convegno IEEE AHS tenutosi a Torino nel June 2013). | 1-gen-2013 | STERPONE, LucaSABENA, DAVIDEULLAH, ANEES + | - |
| On the Optimal Reconfiguration Times for TMR Circuits on SRAM based FPGAs / Sterpone, Luca; Ullah, Anees. - ELETTRONICO. - (2013), pp. 9-14. (Intervento presentato al convegno IEEE AHS tenutosi a Torino nel June 2013). | 1-gen-2013 | STERPONE, LucaULLAH, ANEES | - |
| Phase compensated differential based quadrature direct digital frequency synthesis / Ullah, Anees; Hazrat, Ali; Yasir Ali, Khan; Muhammad, Aamir; Nazim, Ali; K. M., Yahya. - (2012), pp. 1-6. (Intervento presentato al convegno 2012 International Conference on Emerging Technologies (ICET)) [10.1109/ICET.2012.6375485]. | 1-gen-2012 | ULLAH, ANEES + | - |