Archivio Istituzionale della RicercaMIRYALA, SANDEEP
MIRYALA, SANDEEP
Dipartimento di Automatica e Informatica
027634
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.
2015 Rizzo, ROBERTO GIORGIO; Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization
2015 Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amaru', LUCA GAETANO; De Micheli, Giovanni; Gaillardon, Pierre Emmanuel
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates
2014 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions
2013 Miryala, Sandeep; Montazeri, M.; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesInternational Symposium on Quality Electronic Design (ISQED)
2013 Baljit, Kaur; Miryala, Sandeep; S. K., Manhas; Bulusu, Anand
Delay model for reconfigurable logic gates based on graphene PN-junctions
2013 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Exploration of different implementation styles for graphene-based reconfigurable gates
2013 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices
2013 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Bolzani, L.
Power Modeling and Characterization of Graphene-Based Logic Gates
2013 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
IR-Drop Analysis of Graphene-Based Power Distribution Networks
2012 Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation
2012 Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo
NBTI effects on tree-like clock distribution networks
2012 Wei, L.; Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions / Rizzo, R.G., Miryala, S., Calimera, A., Macii, E., Poncino, M.. - ELETTRONICO. - (2015), pp. 253-258. (GLSVLSI '15 Pittsburgh, PA (USA) 20-22 May) [10.1145/2742060.2742099]. | 1-gen-2015 | RIZZO, ROBERTO GIORGIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization / Miryala, S., Tenace, V., Calimera, A., Macii, E., Poncino, M., Amaru', L.G., De Micheli, G., Gaillardon, P.E.. - ELETTRONICO. - (2015), pp. 39-44. (Great Lakes Symposium on VLSI ) [10.1145/2742060.2742098]. | 1-gen-2015 | MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMOAMARU', LUCA GAETANO + | - |
| Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates / Miryala, S., Calimera, A., Macii, E., Poncino, M.. - (2014), pp. 365-371. (DSD-14: IEEE Euromicro Conference on Digital System Design ) [10.1109/DSD.2014.49]. | 1-gen-2014 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions / Miryala, S., Montazeri, M., Calimera, A., Macii, E., Poncino, M.. - (2013), pp. 877-880. (DATE-13: ACM/IEEE Design, Automation & Test in Europe Dresden March) [10.7873/DATE.2013.185]. | 1-gen-2013 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + | - |
| An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesInternational Symposium on Quality Electronic Design (ISQED) / Baljit, K., Miryala, S., S. K., M., Bulusu, A.. - (2013), pp. 665-669. (International Symposium on Quality Electronic Design (ISQED) ) [10.1109/ISQED.2013.6523681]. | 1-gen-2013 | MIRYALA, SANDEEP + | - |
| Delay model for reconfigurable logic gates based on graphene PN-junctions / Miryala, S., Calimera, A., Macii, E., Poncino, M.. - (2013), pp. 227-232. (GLSVLSI-13: ACM Great Lakes Symposium on VLSI Paris May) [10.1145/2483028.2483099]. | 1-gen-2013 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Exploration of different implementation styles for graphene-based reconfigurable gates / Miryala, S., Calimera, A., Macii, E., Poncino, M.. - (2013), pp. 21-24. (ICICDT-13: IEEE International Conference on IC Design & Technology Pavia May) [10.1109/ICICDT.2013.6563294]. | 1-gen-2013 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices / Miryala, S., Calimera, A., Macii, E., Poncino, M., Bolzani, L.. - (2013), pp. 1-6. (LATW-13: IEEE Latin American Test Workshop Cordoba April) [10.1109/LATW.2013.6562674]. | 1-gen-2013 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + | - |
| Power Modeling and Characterization of Graphene-Based Logic Gates / Miryala, S., Calimera, A., Macii, E., Poncino, M.. - (2013), pp. 223-226. (PATMOS-13: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation Karlsruhe September) [10.1109/PATMOS.2013.6662177]. | 1-gen-2013 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| IR-Drop Analysis of Graphene-Based Power Distribution Networks / Miryala, S., Calimera, A., Macii, E., Poncino, M.. - (2012), pp. 81-86. (DATE-12: IEEE Design Automation and Test in Europe Dresden, Germany March 2012). | 1-gen-2012 | MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation / Tenace, V., Miryala, S., Calimera, A., Macii, A., Macii, E., Poncino, M.. - (2012), pp. 1-6. (THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems Budapest September). | 1-gen-2012 | TENACE, VALERIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO | - |
| NBTI effects on tree-like clock distribution networks / Wei, L., Miryala, S., Tenace, V., Calimera, A., Macii, E., Poncino, M.. - (2012), pp. 279-282. (GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI Salt Lake City, Utah May 2012) [10.1145/2206781.2206849]. | 1-gen-2012 | MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + | - |