MIRYALA, SANDEEP

MIRYALA, SANDEEP  

Dipartimento di Automatica e Informatica  

027634  

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Citazione Data di pubblicazione Autori File
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions / Miryala, Sandeep; Montazeri, M.; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2013), pp. 877-880. ((Intervento presentato al convegno DATE-13: ACM/IEEE Design, Automation & Test in Europe tenutosi a Dresden nel March [10.7873/DATE.2013.185]. 1-gen-2013 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + -
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesInternational Symposium on Quality Electronic Design (ISQED) / Baljit, Kaur; Miryala, Sandeep; S. K., Manhas; Bulusu, Anand. - (2013), pp. 665-669. ((Intervento presentato al convegno International Symposium on Quality Electronic Design (ISQED) [10.1109/ISQED.2013.6523681]. 1-gen-2013 MIRYALA, SANDEEP + -
Delay model for reconfigurable logic gates based on graphene PN-junctions / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2013), pp. 227-232. ((Intervento presentato al convegno GLSVLSI-13: ACM Great Lakes Symposium on VLSI tenutosi a Paris nel May [10.1145/2483028.2483099]. 1-gen-2013 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions / Rizzo, ROBERTO GIORGIO; Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2015), pp. 253-258. ((Intervento presentato al convegno GLSVLSI '15 tenutosi a Pittsburgh, PA (USA) nel 20-22 May [10.1145/2742060.2742099]. 1-gen-2015 RIZZO, ROBERTO GIORGIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization / Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amaru', LUCA GAETANO; De Micheli, Giovanni; Gaillardon, Pierre Emmanuel. - ELETTRONICO. - (2015), pp. 39-44. ((Intervento presentato al convegno Great Lakes Symposium on VLSI [10.1145/2742060.2742098]. 1-gen-2015 MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMOAMARU', LUCA GAETANO + gls157s-miryala.pdf
Exploration of different implementation styles for graphene-based reconfigurable gates / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2013), pp. 21-24. ((Intervento presentato al convegno ICICDT-13: IEEE International Conference on IC Design & Technology tenutosi a Pavia nel May [10.1109/ICICDT.2013.6563294]. 1-gen-2013 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Bolzani, L.. - (2013), pp. 1-6. ((Intervento presentato al convegno LATW-13: IEEE Latin American Test Workshop tenutosi a Cordoba nel April [10.1109/LATW.2013.6562674]. 1-gen-2013 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + -
IR-Drop Analysis of Graphene-Based Power Distribution Networks / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2012), pp. 81-86. ((Intervento presentato al convegno DATE-12: IEEE Design Automation and Test in Europe tenutosi a Dresden, Germany nel March 2012. 1-gen-2012 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation / Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2012), pp. 1-6. ((Intervento presentato al convegno THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems tenutosi a Budapest nel September. 1-gen-2012 TENACE, VALERIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO -
NBTI effects on tree-like clock distribution networks / Wei, L.; Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2012), pp. 279-282. ((Intervento presentato al convegno GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI tenutosi a Salt Lake City, Utah nel May 2012 [10.1145/2206781.2206849]. 1-gen-2012 MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + -
Power Modeling and Characterization of Graphene-Based Logic Gates / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2013), pp. 223-226. ((Intervento presentato al convegno PATMOS-13: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation tenutosi a Karlsruhe nel September [10.1109/PATMOS.2013.6662177]. 1-gen-2013 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates / Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2014), pp. 365-371. ((Intervento presentato al convegno DSD-14: IEEE Euromicro Conference on Digital System Design [10.1109/DSD.2014.49]. 1-gen-2014 MIRYALA, SANDEEPCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -