Archivio Istituzionale della RicercaMACCHIARULO, Luca
MACCHIARULO, Luca
Dipartimento di Elettronica (attivo dal 01/01/1900 al 31/12/2011)
003794
Implementation Analysis of NoC: A MPSoC Trace-Driven Approach
2006 Tota, Sergio Vincenzo; Casu, MARIO ROBERTO; Macchiarulo, Luca
A new system design methodology for wire pipelined SoC
2005 Casu, MARIO ROBERTO; Macchiarulo, Luca
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
2005 Casu, MARIO ROBERTO; Macchiarulo, Luca
A New Approach to Latency Insensitive Design
2004 Casu, MARIO ROBERTO; Macchiarulo, Luca
Floorplanning for Throughput
2004 Casu, MARIO ROBERTO; Macchiarulo, Luca
Issues in Implementing Latency Insensitive Protocols
2004 Casu, MARIO ROBERTO; Macchiarulo, Luca
On-Chip Transparent Wire Pipelining (invited paper)
2004 Casu, MARIO ROBERTO; Macchiarulo, Luca
FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
2001 Civera, Pierluigi; Macchiarulo, Luca; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo
A Hybrid Fault Injection Methodology for Real Time Systems
1998 Benso, Alfredo; Civera, Pierluigi; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Ferro, ANTONIO VITO; Macchiarulo, Luca; Violante, Massimo; Prinetto, Paolo Ernesto; R., Ubar; J., Raik
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Implementation Analysis of NoC: A MPSoC Trace-Driven Approach / Tota, Sergio Vincenzo; Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2006), pp. 204-209. ( Great Lakes Symposium on VLSI (GLSVLSI) Philadelphia, PA April 30 - May 01, 2006) [10.1145/1127908.1127957]. | 1-gen-2006 | TOTA, Sergio VincenzoCASU, MARIO ROBERTOMACCHIARULO, Luca | - |
| A new system design methodology for wire pipelined SoC / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2005), pp. 944-945. ( Design, Automation and Test in Europe, 2005. Munich (D) 7-11 March 2005) [10.1109/DATE.2005.25]. | 1-gen-2005 | CASU, MARIO ROBERTOMACCHIARULO, Luca | date05.pdf |
| Floorplan assisted data rate enhancement through wire pipelining: a real assessment / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2005), pp. 121-128. ( International Symposium on Physical Design (ISPD) San Francisco (CA, USA) 3-6 April 2005) [10.1145/1055137.1055163]. | 1-gen-2005 | CASU, MARIO ROBERTOMACCHIARULO, Luca | - |
| A New Approach to Latency Insensitive Design / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 576-581. ( Design Automation Conference (DAC) San Diego (CA, USA) 7-11 June 2004) [10.1145/996566.996725]. | 1-gen-2004 | CASU, MARIO ROBERTOMACCHIARULO, Luca | - |
| Floorplanning for Throughput / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 62-69. ( International Symposium on Physical Design (ISPD) Phoenix (AZ, USA) 18-21 April 2004) [10.1145/981066.981081]. | 1-gen-2004 | CASU, MARIO ROBERTOMACCHIARULO, Luca | - |
| Issues in Implementing Latency Insensitive Protocols / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 1390-1391. ( Design, Automation and Test in Europe, 2004. Paris (F) 16-20 February 2004) [10.1109/DATE.2004.1269102]. | 1-gen-2004 | CASU, MARIO ROBERTOMACCHIARULO, Luca | date04.pdf |
| On-Chip Transparent Wire Pipelining (invited paper) / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 160-167. ( IEEE International Conference on Computer Design (ICCD), 2004 San Jose (CA, USA) 11-13 October 2004) [10.1109/ICCD.2004.1347916]. | 1-gen-2004 | CASU, MARIO ROBERTOMACCHIARULO, Luca | iccd04_paper.pdf |
| FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits / Civera, Pierluigi; Macchiarulo, Luca; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo. - 2147:(2001), pp. 493-502. (Intervento presentato al convegno Field-Programmable Logic and Applications 11th International Conference, FPL 2001 tenutosi a Belfast (GBR) nel Aug. 27-29, 2001) [10.1007/3-540-44687-7_51]. | 1-gen-2001 | CIVERA, PIERLUIGIMACCHIARULO, LucaREBAUDENGO, MaurizioSONZA REORDA, MatteoVIOLANTE, MASSIMO | - |
| A Hybrid Fault Injection Methodology for Real Time Systems / Benso, Alfredo; Civera, Pierluigi; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Ferro, ANTONIO VITO; Macchiarulo, Luca; Violante, Massimo; Prinetto, Paolo Ernesto; R., Ubar; J., Raik. - STAMPA. - (1998), pp. 74-75. ( FTCS-28: 28th Annual International Symposium on Fault-Tolerant Computing Munich (Germany) Jun 23-25, 1998). | 1-gen-1998 | BENSO, AlfredoCIVERA, PIERLUIGIREBAUDENGO, MaurizioSONZA REORDA, MatteoFERRO, ANTONIO VITOMACCHIARULO, LucaVIOLANTE, MASSIMOPRINETTO, Paolo Ernesto + | - |