Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects.

On-Chip Transparent Wire Pipelining (invited paper) / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 160-167. ((Intervento presentato al convegno IEEE International Conference on Computer Design (ICCD), 2004 tenutosi a San Jose (CA, USA) nel 11-13 October 2004 [10.1109/ICCD.2004.1347916].

On-Chip Transparent Wire Pipelining (invited paper)

CASU, MARIO ROBERTO;MACCHIARULO, Luca
2004

Abstract

Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1410347
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