Large Systems-on-Chip (SoC) in advanced technologies run at such high frequencies that the time-of-flight of signals connecting two distant pins in the layout can be higher than the clock period. In order to avoid performance penalties wires are pipelined using latches. However the throughput of the system may be altered due to the presence of loops in the logic netlist. In this paper we address the problem of floorplanning a large design with interconnect pipelining and inserting throughput in the cost function of the floor-planning algorithm. The throughput results obtained on a series of benchmarks are then validated using a simple router that places flipflops along the nets built with an heuristical minimum rectilinear Steiner tree.