The latency insensitive protocols (LIP), which are designed to improve the performance of systems-on-chip, were refined. The refined protocol was validated by using many proof-of-concept examples, that comprised of various combinations of feedforward and feedback topologies. All examples were successfully simulated using VHDL description of all blocks and an event-driven simulator. The results show that the protocol refinement allows precise calculations of important design parameters, like system throughput and transient length.

Issues in Implementing Latency Insensitive Protocols / Casu, MARIO ROBERTO; Macchiarulo, Luca. - STAMPA. - (2004), pp. 1390-1391. ((Intervento presentato al convegno Design, Automation and Test in Europe, 2004. tenutosi a Paris (F) nel 16-20 February 2004 [10.1109/DATE.2004.1269102].

Issues in Implementing Latency Insensitive Protocols

CASU, MARIO ROBERTO;MACCHIARULO, Luca
2004

Abstract

The latency insensitive protocols (LIP), which are designed to improve the performance of systems-on-chip, were refined. The refined protocol was validated by using many proof-of-concept examples, that comprised of various combinations of feedforward and feedback topologies. All examples were successfully simulated using VHDL description of all blocks and an event-driven simulator. The results show that the protocol refinement allows precise calculations of important design parameters, like system throughput and transient length.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/1410346
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