VeriSide-II: Structure-Aware Power Modeling for Side-Channel Analysis at Register Transfer Level

Side-channel attacks exploit data-dependent variations in power consumption to recover secret information from hardware implementations. Detecting leakage at early design stages is critical, as post-synthesis or silicon-level fixes are costly and limited. At the RTL level, power is commonly approximated using switching-activity-based proxies, such as Hamming Weight (HW) or Hamming Distance (HD), which effectively model the activity factor in the dynamic power equation. Prior work has focused on scalable extraction and statistical analysis of such traces, without explicitly considering the device structural properties that may influence the effective capacitive term. This work investigates the integration of structural information at RTL to better approximate the capacitive component of dynamic power. VeriSide-II introduces a structure-aware proxy that augments switching activity with fan-out and combinational depth to form a more accurate capacitance model. Validation against post-synthesis gate-level power achieves approximately 93% correlation. As a second validation, a comparison against FPGA measurements shows up to a 10% improvement in diagonal-band correlation over activity-only formulations, while preserving leakage alignment under representative CPA experiments. These results experimentally demonstrate that incorporating structural awareness at RTL improves power-proxy fidelity and strengthens consistency between simulation-based and hardware-observed leakage, enabling more reliable early-stage side-channel assessment.