Mitigating Cross-Domain SEU Corruption in FPGA-Based AI Accelerators for Space Applications

SRAM-based FPGAs have become increasingly popular for missioncritical applications due to their high computational performance and reconfigurability, particularly in AI-drivenworkloads. However, their vulnerability to radiation-induced faults, especially Single Event Upsets (SEUs), demands robust mitigation strategies. While techniques like modular redundancy offer protection, they remain susceptible to cross-domain errors that can simultaneously affect multiple cores. This paper explores the impact of placement-level isolation as a mitigation strategy for SEUs in multi-core FPGA designs. We propose and evaluate three layout configurations with varying levels of resource isolation, implemented on a Xilinx UltraScale+ device. The designs were subjected to high-energy proton irradiation to assess their fault resilience. Results show that custom placement strategies beyond default vendor tools can improve resistance to cross-domain soft errors by up to 36%, offering a promising complement to traditional fault-tolerant methods.