Evaluating the Impact of Aging on Path-Delay Self-Test Libraries

Self-Test Libraries (STLs) developed for path-delay faults are crucial to ensure the reliability of modern digital integrated circuits, since they represent a widely adopted solution to detect in-field faults occurring during the operational phase, e.g., due to aging. However, physical parameters may shift over time, leading to changes in device behavior and potential failures with respect to end of manufacturing. This is especially crucial in safety-critical applications such as those adopted in automotive systems. The main objective of this paper is to assess the quality of STLs over time by monitoring how critical paths change due to aging effects and evaluating the fault coverage of STLs. An automatic framework is proposed to age an integrated circuit starting from a limited set of physical data related to the adopted technology. The insights gained from this approach will allow test engineers to harden STLs and ensure that strict reliability requirements are always met.