Recently, the adoption of Cell-Aware Testing (CAT) has become an option for an increasing number of semiconductor companies. Typically, CAT is adopted in the context of scan chain tests, and patterns are generated with an Automatic Test Pattern Generation (ATPG) tool. Moreover, past studies have extensively shown the capability of CAT to identify the microchips’ physical defects that would otherwise remain undetected using traditional fault models, only. However, due to the higher number of patterns generated, an improper CAT-related ATPG flow can lead to a longer test application time. This means higher costs for semiconductor companies, thus reducing the advantages of CAT. The aim of this paper is to overview different ATPG flows supporting CAT, showing advantages and disadvantages of each approach. Each flow is evaluated together with traditional and cell-aware fault models in terms of achievable fault coverage and pattern count. The experimental results are presented through a wide range of open-source benchmarks using a proprietary industrial technology library.

A comparative overview of ATPG flows targeting traditional and cell-aware fault models / Mirabella, Nunzio; Floridia, Andrea; Cantoro, Riccardo; Grosso, Michelangelo; Sonza Reorda, Matteo. - ELETTRONICO. - (In corso di stampa), pp. 1-4. ((Intervento presentato al convegno 29th IEEE International Conference on Electronics Circuits and Systems (ICECS) tenutosi a Glasgow nel 24th - 26th October 2022.

A comparative overview of ATPG flows targeting traditional and cell-aware fault models

Mirabella, Nunzio;Floridia, Andrea;Cantoro, Riccardo;Grosso, Michelangelo;Sonza Reorda, Matteo
In corso di stampa

Abstract

Recently, the adoption of Cell-Aware Testing (CAT) has become an option for an increasing number of semiconductor companies. Typically, CAT is adopted in the context of scan chain tests, and patterns are generated with an Automatic Test Pattern Generation (ATPG) tool. Moreover, past studies have extensively shown the capability of CAT to identify the microchips’ physical defects that would otherwise remain undetected using traditional fault models, only. However, due to the higher number of patterns generated, an improper CAT-related ATPG flow can lead to a longer test application time. This means higher costs for semiconductor companies, thus reducing the advantages of CAT. The aim of this paper is to overview different ATPG flows supporting CAT, showing advantages and disadvantages of each approach. Each flow is evaluated together with traditional and cell-aware fault models in terms of achievable fault coverage and pattern count. The experimental results are presented through a wide range of open-source benchmarks using a proprietary industrial technology library.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2971532