Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement / Cantoro, Riccardo; Girard, Patrick; Masante, Riccardo; Sartoni, Sandro; Reorda, Matteo Sonza; Virazel, Arnaud. - (2021), pp. 1-4. ((Intervento presentato al convegno 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) nel 28-30 June 2021 [10.1109/IOLTS52814.2021.9486711].

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Cantoro, Riccardo;Masante, Riccardo;Sartoni, Sandro;Reorda, Matteo Sonza;
2021

Abstract

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.
978-1-6654-3370-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2915694