Traditionally, the usage of caches and deterministic execution of on-line self-test procedures have been considered two mutually exclusive concepts. At the same time, software executed in a multi-core context suffers of a limited timing predictability due to the higher system bus contention. When dealing with selftest procedures, this higher contention might lead to a fluctuating fault coverage or even the failure of some test programs. This paper presents a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures in multi-core systems. The proposed strategy is applied to two representative modules negatively affected by a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit. The experiments illustrate that it is possible to achieve a stable execution while also improving the state-of-the-art approaches for the on-line testing of embedded microprocessors. The effectiveness of the methodology was assessed on all the three cores of a multi-core industrial System- on-Chip intended for automotive ASIL D applications.

Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips / Floridia, Andrea; Carmona, Tzamn Melendez; Piumatti, Davide; Ruospo, Annachiara; Sanchez, Ernesto; Luca, Sergio De; Martorana, Rosario; Pernice, Mose Alessandro. - ELETTRONICO. - (2020), pp. 1235-1240. ((Intervento presentato al convegno 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) tenutosi a Grenoble, France nel 9-13 March, 2020 [10.23919/DATE48585.2020.9116239].

Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips

Floridia, Andrea;Piumatti, Davide;Ruospo, Annachiara;Sanchez, Ernesto;
2020

Abstract

Traditionally, the usage of caches and deterministic execution of on-line self-test procedures have been considered two mutually exclusive concepts. At the same time, software executed in a multi-core context suffers of a limited timing predictability due to the higher system bus contention. When dealing with selftest procedures, this higher contention might lead to a fluctuating fault coverage or even the failure of some test programs. This paper presents a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures in multi-core systems. The proposed strategy is applied to two representative modules negatively affected by a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit. The experiments illustrate that it is possible to achieve a stable execution while also improving the state-of-the-art approaches for the on-line testing of embedded microprocessors. The effectiveness of the methodology was assessed on all the three cores of a multi-core industrial System- on-Chip intended for automotive ASIL D applications.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2837295