On the Optimization of SBST Test Program Compaction

Due to the increasing adoption of SBST solutions for the end-of-manufacturing and in-field test of SoC devices, the need for effective techniques able to reduce the duration of existing test programs becomes more urgent. Previous works demonstrated that this task is highly computational intensive and it is beneficial to partition it, e.g., addressing the test program for one hardware module at a time. However, existing techniques may become completely ineffective when dealing with some faults, which relate to memory addresses. This paper clarifies this issue and proposes some possible solutions. Their effectiveness is experimentally demonstrated resorting to the OR1200 pipelined processor.