Archivio Istituzionale della RicercaPARESCHI, FABIO
PARESCHI, FABIO
Dipartimento di Elettronica e Telecomunicazioni
049471
A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation
2008 Pareschi, F.; Setti, G.; Rovatti, R.
A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation
2010 Pareschi, F.; Setti, G.; Rovatti., R.
A 65nm continuous-time sigma-delta modulator with limited OTA DC gain compensation
2020 Gonzalez-Diaz, V. R.; Pareschi, F.
A case study in low-complexity ECG signal encoding: How compressing is compressed sensing?
2015 Cambareri, Valerio; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A Comparison between Class-E DC-DC Design Methodologies for Wireless Power Transfer
2021 Celentano, A.; Pareschi, F.; Valente, V.; Rovatti, R.; Serdijn, W. A.; Setti, G.
A fast chaos-based true random number generator for cryptographic applications
2006 Pareschi, F.; Rovatti, R.; Setti, G.
A first implementation of a semi-analytically designed class-E resonant DC-DC converter
2015 Bertoni, Nicola; Frattini, Giovanni; Albertini, Pierluigi; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A fully CMOS true random number generator based on hidden attractor hyperchaotic system
2020 Nguyen, N.; Kaddoum, G.; Pareschi, F.; Rovatti, R.; Setti, G.
A High-level Implementation Framework for Non-Recurrent Artificial Neural Networks on FPGA
2019 Prono, Luciano; Marchioni, A.; Mangia, M.; Pareschi, F.; Rovatti, R.; Setti, G.
A macro-model for the efficient simulation of an ADC-based RNG
2005 Pareschi, F.; Setti, G.; Rovatti, R.
A Methodology for Practical Design and Optimization of Class-E DC-DC Resonant Converters
2020 Celentano, A; Pareschi, F; Gozalez-Diaz, Vr; Rovatti, R; Setti, G
A new semi-analytic approach for class-E resonant DC-DC converter design
2015 Bertoni, Nicola; Frattini, Giovanni; Massolini, Roberto; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A Non-conventional Sum-and-Max based Neural Network layer for Low Power Classification
2022 Prono, Luciano; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC
2020 Paolino, C.; Prono, L.; Pareschi, F.; Mangia, M.; Rovatti, R.; Setti, G.
A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities
2019 Paolino, Carmine; Pareschi, F.; Mangia, M.; Rovatti, R.; Setti, G.
A Pragmatic Look at Some Compressive Sensing Architectures With Saturation and Quantization
2012 Haboba, Javier; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A pseudorandom number generator based on time-variant recursion of accumulators
2011 Gonzalez-Diaz, Victor R.; Pareschi, Fabio; Setti, Gianluca; Maloberti, Franco
A rakeness-based design flow for Analog-to-Information conversion by Compressive Sensing
2013 Cambareri, Valerio; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca
A Soft-Defined Pulse Width Modulation Approach - Part I: Principles
2015 Caporale, Salvatore; Pareschi, Fabio; Cambareri, Valerio; Rovatti, Riccardo; Setti, Gianluca
A Soft-Defined Pulse Width Modulation Approach-Part II: System Modeling
2015 Caporale, Salvatore; Pareschi, Fabio; Cambareri, Valerio; Rovatti, Riccardo; Setti, Gianluca
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation / Pareschi, F.; Setti, G.; Rovatti, R.. - STAMPA. - (2008), pp. 451-454. (Intervento presentato al convegno IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 tenutosi a San Jose, CA, usa nel 2008) [10.1109/CICC.2008.4672118]. | 1-gen-2008 | Pareschi F.Setti G. + | 116.pdf; CICC2008-pll4g.pdf |
| A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation / Pareschi, F.; Setti, G.; Rovatti., R.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - STAMPA. - 57:10(2010), pp. 2577-2587. [10.1109/TCSI.2010.2048771] | 1-gen-2010 | F. PareschiG. Setti + | 9-TCAS-I-EMI-SATA.pdf |
| A 65nm continuous-time sigma-delta modulator with limited OTA DC gain compensation / Gonzalez-Diaz, V. R.; Pareschi, F.. - In: IEEE ACCESS. - ISSN 2169-3536. - STAMPA. - 8:(2020), pp. 36464-36475. [10.1109/ACCESS.2020.2975601] | 1-gen-2020 | Pareschi F. + | 09006892.pdf |
| A case study in low-complexity ECG signal encoding: How compressing is compressed sensing? / Cambareri, Valerio; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - In: IEEE SIGNAL PROCESSING LETTERS. - ISSN 1070-9908. - STAMPA. - 22:10(2015), pp. 1743-1747. [10.1109/LSP.2015.2428431] | 1-gen-2015 | Pareschi FabioSetti Gianluca + | LSP2428431.pdf; 07100859.pdf |
| A Comparison between Class-E DC-DC Design Methodologies for Wireless Power Transfer / Celentano, A.; Pareschi, F.; Valente, V.; Rovatti, R.; Serdijn, W. A.; Setti, G.. - STAMPA. - 2021:(2021), pp. 71-74. (Intervento presentato al convegno 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 tenutosi a Lansing, MI, USA nel 2021) [10.1109/MWSCAS47672.2021.9531712]. | 1-gen-2021 | Celentano A.Pareschi F.Setti G. + | mwscas.pdf; A_Comparison_between_Class-E_DC-DC_Design_Methodologies_for_Wireless_Power_Transfer.pdf |
| A fast chaos-based true random number generator for cryptographic applications / Pareschi, F.; Rovatti, R.; Setti, G.. - STAMPA. - (2006), pp. 130-133. (Intervento presentato al convegno 32nd European Solid-State Circuits Conference (ESSCIRC2006) tenutosi a Montreux, Switzerland nel September 2006) [10.1109/ESSCIR.2006.307548]. | 1-gen-2006 | F. PARESCHISETTI G. + | ESSCIRC2006.pdf; esscirc2006-RNG.pdf |
| A first implementation of a semi-analytically designed class-E resonant DC-DC converter / Bertoni, Nicola; Frattini, Giovanni; Albertini, Pierluigi; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - STAMPA. - (2015), pp. 221-224. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems, ISCAS 2015 tenutosi a Lisbon; Portugal nel 24 May 2015 through 27 May 2015) [10.1109/ISCAS.2015.7168610]. | 1-gen-2015 | Pareschi FabioSetti Gianluca + | ISCAS2015-ClassE-pt2.pdf; A_first_implementation_of_a_semi-analytically_designed_class-E_resonant_DC-DC_converter.pdf |
| A fully CMOS true random number generator based on hidden attractor hyperchaotic system / Nguyen, N.; Kaddoum, G.; Pareschi, F.; Rovatti, R.; Setti, G.. - In: NONLINEAR DYNAMICS. - ISSN 0924-090X. - STAMPA. - 102:4(2020), pp. 2887-2904. [10.1007/s11071-020-06017-3] | 1-gen-2020 | Pareschi F.Setti G. + | Nguyen2020_Article_AFullyCMOSTrueRandomNumberGene.pdf |
| A High-level Implementation Framework for Non-Recurrent Artificial Neural Networks on FPGA / Prono, Luciano; Marchioni, A.; Mangia, M.; Pareschi, F.; Rovatti, R.; Setti, G.. - STAMPA. - 2019:(2019), pp. 77-80. (Intervento presentato al convegno 15th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2019 tenutosi a Lausanne (Switzerland) nel July 15-18, 2019) [10.1109/PRIME.2019.8787830]. | 1-gen-2019 | PRONO, LUCIANOPareschi F.Setti G. + | 08787830.pdf; PRIME2019-Prono.pdf |
| A macro-model for the efficient simulation of an ADC-based RNG / Pareschi, F.; Setti, G.; Rovatti, R.. - STAMPA. - (2005), pp. 4349-4352. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 tenutosi a Kobe, jpn nel May 23-26, 2005) [10.1109/ISCAS.2005.1465594]. | 1-gen-2005 | Pareschi F.Setti G. + | C1L-N3.pdf; ISCAS2005-macromodel.pdf |
| A Methodology for Practical Design and Optimization of Class-E DC-DC Resonant Converters / Celentano, A; Pareschi, F; Gozalez-Diaz, Vr; Rovatti, R; Setti, G. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 8:(2020), pp. 205568-205589. [10.1109/ACCESS.2020.3035507] | 1-gen-2020 | Celentano, APareschi, FSetti, G + | 09247201.pdf |
| A new semi-analytic approach for class-E resonant DC-DC converter design / Bertoni, Nicola; Frattini, Giovanni; Massolini, Roberto; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - STAMPA. - (2015), pp. 2485-2488. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems, ISCAS 2015 tenutosi a Lisbon; Portugal nel 24 May 2015 through 27 May 2015) [10.1109/ISCAS.2015.7169189]. | 1-gen-2015 | Pareschi FabioSetti Gianluca + | Setti-Anewsemi-analytic-pdf.pdf; ISCAS2015-ClassE-pt1.pdf |
| A Non-conventional Sum-and-Max based Neural Network layer for Low Power Classification / Prono, Luciano; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - STAMPA. - (2022), pp. 712-716. (Intervento presentato al convegno 2022 International Symposium on Circuits and Systems tenutosi a Austin, Texas nel May 28 - June 1, 2022) [10.1109/ISCAS48785.2022.9937576]. | 1-gen-2022 | Prono, LucianoPareschi, FabioSetti, Gianluca + | iscas2022-samnmax.pdf; A_Non-conventional_Sum-and-Max_based_Neural_Network_layer_for_Low_Power_Classification.pdf |
| A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC / Paolino, C.; Prono, L.; Pareschi, F.; Mangia, M.; Rovatti, R.; Setti, G.. - In: INTEGRATION. - ISSN 0167-9260. - STAMPA. - 75:(2020), pp. 40-51. [10.1016/j.vlsi.2020.05.007] | 1-gen-2020 | Paolino C.Prono L.Pareschi F.Setti G. + | SAR_CS___PRIME_follow_up.pdf; 1-s2.0-S016792601930553X-main.pdf |
| A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities / Paolino, Carmine; Pareschi, F.; Mangia, M.; Rovatti, R.; Setti, G.. - STAMPA. - 2019:(2019), pp. 133-136. (Intervento presentato al convegno 15th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2019 tenutosi a Lausanne (Switzerland) nel July 15-18, 2019) [10.1109/PRIME.2019.8787816]. | 1-gen-2019 | PAOLINO, CARMINEPareschi F.Setti G. + | 08787816.pdf; PRIME2019-Paolino.pdf |
| A Pragmatic Look at Some Compressive Sensing Architectures With Saturation and Quantization / Haboba, Javier; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - In: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS. - ISSN 2156-3357. - STAMPA. - 2:(2012), pp. 443-459. [10.1109/JETCAS.2012.2220392] | 1-gen-2012 | Fabio PareschiGianluca Setti + | A_Pragmatic_Look_at_Some_Compressive_Sensing_Architectures_With_Saturation_and_Quantization.pdf |
| A pseudorandom number generator based on time-variant recursion of accumulators / Gonzalez-Diaz, Victor R.; Pareschi, Fabio; Setti, Gianluca; Maloberti, Franco. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - 58:9(2011), pp. 580-584. [10.1109/TCSII.2011.2161165] | 1-gen-2011 | Fabio PareschiGianluca Setti + | TCAS-II-2012-TimeVariantPRNG.pdf; Pareschi-Apseudorandom.pdf |
| A rakeness-based design flow for Analog-to-Information conversion by Compressive Sensing / Cambareri, Valerio; Mangia, Mauro; Pareschi, Fabio; Rovatti, Riccardo; Setti, Gianluca. - STAMPA. - (2013), pp. 1360-1363. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems (ISCAS2013) tenutosi a Beijing nel May 2013) [10.1109/ISCAS.2013.6572107]. | 1-gen-2013 | Fabio PareschiGianluca Setti + | iscas2013-designflow.pdf; B4L-B3-1793.pdf |
| A Soft-Defined Pulse Width Modulation Approach - Part I: Principles / Caporale, Salvatore; Pareschi, Fabio; Cambareri, Valerio; Rovatti, Riccardo; Setti, Gianluca. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - STAMPA. - 62:9(2015), pp. 2280-2289. [10.1109/TCSI.2015.2459555] | 1-gen-2015 | Pareschi FabioSetti Gianluca + | Setti-Asoft-defined1.pdf |
| A Soft-Defined Pulse Width Modulation Approach-Part II: System Modeling / Caporale, Salvatore; Pareschi, Fabio; Cambareri, Valerio; Rovatti, Riccardo; Setti, Gianluca. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - STAMPA. - 62:9(2015), pp. 2290-2300. [10.1109/TCSI.2015.2459556] | 1-gen-2015 | Pareschi FabioSetti Gianluca + | Setti-Asoft-defined.pdf |