In this brief we propose a novel ByPass (BP) circuit that overcomes the voltage regulation limit in the Ripple Based Constant On-Time (RB-COT) Buck converters due to intrinsic presence of a minimum achievable OFF time. The BP stage is conceived to be embedded in the RB-COT modulator located within the converter feedback loop, and only intervening when the minimum OFF time condition is reached. The latter implies that the COT modulator saturates, and consequently, the output voltage regulation of the converter is no longer guaranteed. Conversely, the BP stage does not affect the behavior of the circuit when it operates in normal regulating condition. The effectiveness of the proposed BP stage is confirmed through both transistor-level simulation results derived from the SPICE platform and experimental measurements on a integrated circuit prototype implemented in a 0.18 um Bipolar-CMOS-DMOS process.

A Novel Bypass Architecture for RB-COT Buck Converters / Gabriele, Francesco; Gisonno, Samuele; Fiori, Filippo; Lena, Davide; Musumeci, Salvatore Rosario; Pareschi, Fabio; Setti, Gianluca. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - (2025). [10.1109/tcsii.2025.3555695]

A Novel Bypass Architecture for RB-COT Buck Converters

Gabriele, Francesco;Pareschi, Fabio;Setti, Gianluca
2025

Abstract

In this brief we propose a novel ByPass (BP) circuit that overcomes the voltage regulation limit in the Ripple Based Constant On-Time (RB-COT) Buck converters due to intrinsic presence of a minimum achievable OFF time. The BP stage is conceived to be embedded in the RB-COT modulator located within the converter feedback loop, and only intervening when the minimum OFF time condition is reached. The latter implies that the COT modulator saturates, and consequently, the output voltage regulation of the converter is no longer guaranteed. Conversely, the BP stage does not affect the behavior of the circuit when it operates in normal regulating condition. The effectiveness of the proposed BP stage is confirmed through both transistor-level simulation results derived from the SPICE platform and experimental measurements on a integrated circuit prototype implemented in a 0.18 um Bipolar-CMOS-DMOS process.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2998906