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High speed VLSI architecture for finding the first W maximum/minimum values
2016 Xiao, G.; Ahmad, W.; Zaidi, S. A. A.; Roch, M. R.; Causapruno, G.
VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard
2016 Xiao, Guoping
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values
2014 Xiao, Guoping; Martina, Maurizio; Masera, Guido; Piccinini, Gianluca
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| High speed VLSI architecture for finding the first W maximum/minimum values / Xiao, G.; Ahmad, W.; Zaidi, S. A. A.; Roch, M. R.; Causapruno, G.. - ELETTRONICO. - 351:(2016), pp. 35-41. (Intervento presentato al convegno Conference on Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2014 tenutosi a ita nel 2014) [10.1007/978-3-319-20227-3_5]. | 1-gen-2016 | Xiao G.Ahmad W.Roch M. R.Causapruno G. + | - |
| VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard / Xiao, Guoping. - (2016). [10.6092/polito/porto/2644058] | 1-gen-2016 | XIAO, GUOPING | PhD Dissertation Guoping XIAO.pdf |
| A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values / Xiao, Guoping; Martina, Maurizio; Masera, Guido; Piccinini, Gianluca. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - 61:11(2014), pp. 890-894. [10.1109/TCSII.2014.2350333] | 1-gen-2014 | XIAO, GUOPINGMARTINA, MAURIZIOMASERA, GuidoPICCININI, GIANLUCA | papero.pdf |