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EnglishVLSI architectures for finding the first W maximum/minimum values are highly demanded in the fields of K-best MIMO detector, non-binary LDPC decoder and product-code decoder. In this paper, a VLSI architecture based on parallel comparing scheme is explored for finding the first W maximum/minimum values from M inputs. The place and route results using a TSMC 90-nm CMOS technology show that, despite some hardware cost, it achieves on average a 3.6x faster speed performance compared to the existing partial sorting architectures.
High speed VLSI architecture for finding the first W maximum/minimum values / Xiao, G.; Ahmad, W.; Zaidi, S. A. A.; Roch, M. R.; Causapruno, G.. - 351(2016), pp. 35-41. ((Intervento presentato al convegno Conference on Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2014 tenutosi a ita nel 2014.
| Titolo: | High speed VLSI architecture for finding the first W maximum/minimum values | |
| Autori: | ||
| Data di pubblicazione: | 2016 | |
| Serie: | ||
| Abstract: | VLSI architectures for finding the first W maximum/minimum values are highly demanded in the fiel...ds of K-best MIMO detector, non-binary LDPC decoder and product-code decoder. In this paper, a VLSI architecture based on parallel comparing scheme is explored for finding the first W maximum/minimum values from M inputs. The place and route results using a TSMC 90-nm CMOS technology show that, despite some hardware cost, it achieves on average a 3.6x faster speed performance compared to the existing partial sorting architectures. | |
| ISBN: | 978-3-319-20226-6 978-3-319-20227-3 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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