statistiche ricercatore

Nazione	#
US - Stati Uniti d'America	3.007
IT - Italia	646
GB - Regno Unito	344
DE - Germania	332
FR - Francia	308
SG - Singapore	270
VN - Vietnam	216
CN - Cina	206
RU - Federazione Russa	112
UA - Ucraina	101
NL - Olanda	73
BR - Brasile	64
HK - Hong Kong	51
TR - Turchia	46
GR - Grecia	44
KR - Corea	44
SE - Svezia	44
CA - Canada	41
JP - Giappone	38
CH - Svizzera	28
IE - Irlanda	28
IN - India	27
FI - Finlandia	23
AT - Austria	20
JO - Giordania	14
ID - Indonesia	10
ZA - Sudafrica	10
BD - Bangladesh	8
ES - Italia	8
PL - Polonia	8
TH - Thailandia	8
TW - Taiwan	7
BE - Belgio	6
CL - Cile	6
IQ - Iraq	6
PH - Filippine	5
AE - Emirati Arabi Uniti	4
IR - Iran	4
RO - Romania	4
SN - Senegal	4
AU - Australia	3
DK - Danimarca	3
IL - Israele	3
SA - Arabia Saudita	3
VE - Venezuela	3
BG - Bulgaria	2
BY - Bielorussia	2
GH - Ghana	2
KZ - Kazakistan	2
LT - Lituania	2
LV - Lettonia	2
NO - Norvegia	2
PK - Pakistan	2
AL - Albania	1
AP - ???statistics.table.value.countryCode.AP???	1
AR - Argentina	1
AZ - Azerbaigian	1
CZ - Repubblica Ceca	1
EC - Ecuador	1
EE - Estonia	1
EU - Europa	1
HN - Honduras	1
HU - Ungheria	1
KW - Kuwait	1
MA - Marocco	1
MD - Moldavia	1
MX - Messico	1
MY - Malesia	1
NP - Nepal	1
NZ - Nuova Zelanda	1
PY - Paraguay	1
SI - Slovenia	1
TN - Tunisia	1
TT - Trinidad e Tobago	1
UZ - Uzbekistan	1
Totale	6.278

Nome	#
A Hybrid Fault Injection Methodology for Real Time Systems	657
A case study for NoC based homogeneous MPSoC architectures	649
FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits	565
Adaptive Latency Insensitive Protocols	551
Throughput-driven floorplanning with wire pipelining.	545
A new system design methodology for wire pipelined SoC	494
Floorplanning with wire pipelining in adaptive communication channels	481
Issues in Implementing Latency Insensitive Protocols	447
Adaptive Latency Insensitive Protocols andElastic Circuits with Early Evaluation: A Comparative Analysis	422
On-Chip Transparent Wire Pipelining (invited paper)	343
A New Approach to Latency Insensitive Design	321
Implementation Analysis of NoC: A MPSoC Trace-Driven Approach	310
Floorplanning for Throughput	292
Floorplan assisted data rate enhancement through wire pipelining: a real assessment	259
Totale	6.336

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2020/2021	20	0	0	0	0	0	0	0	0	0	0	0	20
2021/2022	224	6	21	0	5	14	25	24	9	9	24	39	48
2022/2023	768	31	64	17	43	36	51	399	21	50	5	25	26
2023/2024	88	12	7	4	3	13	14	5	1	2	4	6	17
2024/2025	330	1	51	15	30	36	22	5	30	51	30	36	23
2025/2026	942	35	52	31	90	93	77	140	79	214	84	18	29
Totale													6.336

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