Vectorized in-Place CRC: a Zero Memory-Overhead Fault Detection Scheme for QNNs on RISC-V

Reliability against memory-induced transient faults is a critical requirement for quantized neural networks (QNNs) deployed in safety-critical edge environments. This paper proposes an in-place fault detection strategy that embeds Cyclic Redundancy Check (CRC) codes directly into the Least Significant Bits (LSBs) of 8-bit quantized weights, achieving zero storage overhead by repurposing weight precision for granular reliability. The scheme leverages a vectorized routine optimized for the RISC-V Ibex architecture, exploiting SIMD-within-a-register (SWAR) techniques to validate weights. Cycle-accurate simulations on the lowRISC Ibex core (RV32IMC) experimentally demonstrate that the proposed CRC-Vectorized approach achieves a throughput of 9 clock cycles per weight, outperforming its results software-based ECC counterpart by 10%. Experimental across four image classification workloads on the CIFAR-10 dataset show that while this accuracy-for-reliability trade-off entails an average accuracy drop of 6.72% (using CRC-3), it provides robust fault coverage: 100% detection for single-bit flips and 3-bit burst errors, and 92.22% for double-bit errors. This solution shows an excellent reliability-performance balance, suitable for resource-constrained edge devices.