The rising density and complexity of domain-specific accelerators make conventional design space exploration strategies prohibitively expensive. These costs further escalate when non-functional properties, such as resilience, must be assessed for safety-critical applications, highlighting the need for innovative early-stage evaluation frameworks. This work investigates methods for early estimation of design and resilience features in large hardware accelerators for edge computing and machine learning (e.g., vector processors, tensor cores, and stereo vision engines). We first outline design space exploration challenges at the micro-architectural level for configurable vector processors. We then assess the use of open-source hyperscaler frameworks to analyze fine-grained functional and non-functional properties of large accelerators via simulation and emulation. Results show that such frameworks are feasible solutions and provide a viable path to reducing the computational costs of early characterization and evaluation.
Analyzing hardware accelerators’ reliability: from design exploration to fast evaluation with hyperscalers / Guerrero-Balaguera, Juan-David; Limas Sierra, Robert; Vilar De Farias, Gustavo; Abed, Sergiu-Mohamed; Bagbaba, Ahmet Cagri; Rodriguez Condia, Josie E.. - ELETTRONICO. - (2026). ( 2026 17th IEEE Latin American Symposium on Circuits and Systems Arequipa (PE) 24-27 February 2026) [10.1109/LASCAS67804.2026.11457105].
Analyzing hardware accelerators’ reliability: from design exploration to fast evaluation with hyperscalers
Guerrero-Balaguera, Juan-David;Limas Sierra, Robert;Vilar de Farias, Gustavo;Abed, Sergiu-Mohamed;Rodriguez Condia, Josie E.
2026
Abstract
The rising density and complexity of domain-specific accelerators make conventional design space exploration strategies prohibitively expensive. These costs further escalate when non-functional properties, such as resilience, must be assessed for safety-critical applications, highlighting the need for innovative early-stage evaluation frameworks. This work investigates methods for early estimation of design and resilience features in large hardware accelerators for edge computing and machine learning (e.g., vector processors, tensor cores, and stereo vision engines). We first outline design space exploration challenges at the micro-architectural level for configurable vector processors. We then assess the use of open-source hyperscaler frameworks to analyze fine-grained functional and non-functional properties of large accelerators via simulation and emulation. Results show that such frameworks are feasible solutions and provide a viable path to reducing the computational costs of early characterization and evaluation.| File | Dimensione | Formato | |
|---|---|---|---|
|
lascas_final.pdf
accesso aperto
Tipologia:
2. Post-print / Author's Accepted Manuscript
Licenza:
Pubblico - Tutti i diritti riservati
Dimensione
421.27 kB
Formato
Adobe PDF
|
421.27 kB | Adobe PDF | Visualizza/Apri |
|
Analyzing_Hardware_Accelerators_Reliability_From_Design_Exploration_to_Fast_Evaluation_with_Hyperscalers.pdf
accesso riservato
Tipologia:
2a Post-print versione editoriale / Version of Record
Licenza:
Non Pubblico - Accesso privato/ristretto
Dimensione
455.59 kB
Formato
Adobe PDF
|
455.59 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/3007099
