System-Level Test techniques for Automotive SoCs

Traditional structural tests do not provide comprehensive coverage of all possible faults in automotive System-on-Chips (SoCs). To address these gaps, the manufacturing test flow now incorporates System-Level Test (SLT), an additional holistic test phase that executes advanced functional test programs. This research advances SLT methodologies by introducing a stress-optimization approach that targets critical, non-uniformly stressed areas, complementing structural stress methods. It also provides practical guidelines for developing SLT suites that effectively test SoC communication peripherals. Additionally, automated SLT workload generation techniques leverage graph-based SoC abstractions and Device Tree Source (DTS) files to reduce manual effort. Furthermore, grading methodologies are proposed to evaluate SLT effectiveness using high-level metrics derived from instruction traces, enabling early feedback without exhaustive fault simulation. The proposed methods are validated on a 40nm automotive SoC, manufactured by STMicroelectronics, with approximately 20 million logic gates, using a low-cost, FPGA-based modular tester. Experimental results demonstrate that SLT suites can significantly enhance the quality and reliability of automotive SoCs. Collectively, these contributions make SLT more scalable, automated, and effective, meeting stringent automotive quality standards and enabling broader application in domains such as data center processors.