High-Precision Time Measurement on FPGA: An Optimized TDC Approach

Time-To-Digital Converters (TDCs) are crucial for high-precision time measurements in applications like particle physics and medical imaging. While ASIC-based TDCs offer high accuracy, they lack flexibility. Implementing TDC on FPGA platforms faces significant challenges due to the digital nature of these devices. In literature, TDC designs are often presented in theoretical terms, with limited implementation details. Practical realizations frequently require adapting and refining the original concepts to match the specific device architecture and capability. The custom placement and routing constraints, or manual instantiation of primitive elements, are rarely discussed but are critical for achieving reliable and reproducible results. The omission of these aspects contributes to the gap between theoretical proposals and working hardware implementations. This work addresses this gap by presenting a fully implemented and FPGA-optimized TDC based on a tapped delay line (TDL) architecture, achieving 6 ps resolution and 30 ps precision on an AMD Kintex UltraScale FPGA, discussing detailed low-level optimizations, making it not only a high-performance solution but also a concrete reference for future implementations.