In the past years, the complexity of Automotive System-on-Chips (SoCs) has risen dramatically, mainly dictated by the increasing application requirements. As the complexity increases, safety standards, such as ISO 26262, impose quality requirements on manufactured devices. Manufactured SoCs go through a manufacturing test flow where, at every step, a set of tests is conducted to verify that the SoCs are manufactured correctly. Although the manufacturing test flow has been stabilized among companies, with the rising complexity of SoCs, the test pace is hard to keep. Consequently, in the last decade, many companies introduced the so-called System-Level Test (SLT) as an additional test step. SLT could be combined with other test steps in order to screen faulty SoCs effectively. Industrial semiconductor testers are available in the market. However, to the best of our knowledge, in the state-of-the-art FPGA-based semiconductor tester, no tester can combine different advanced test strategies, such as advanced functional applications (SLT) and structural tests (scan-based). The proposed FPGA-based Test Equipment aims to overcome the limitations in Research Labs (at universities or in companies), for failure analysis and test-flow prototyping; since an industrial tester, called Automatic Test Equipment (ATE) is expensive and requires physical space. Experimental results show how the hardware is carried out on an FPGA platform with its performance and utilization factor. Meanwhile, the execution time of the software is profiled. Using an industrial Automotive SoC, it shows how the proposed semiconductor tester enables the development of different test strategies.

A Flexible FPGA-based Test Equipment for Enabling Out-of-Production Manufacturing Test Flow of Digital Systems / DI GRUTTOLA GIARDINO, Nicola; Angione, Francesco; Bernardi, Paolo; Foscale, Tommaso; Bertani and Vincenzo Tancorre, Claudia. - (2024). (Intervento presentato al convegno International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) tenutosi a Didcot (UK) nel 08-10 October 2024) [10.1109/DFT63277.2024.10753536].

A Flexible FPGA-based Test Equipment for Enabling Out-of-Production Manufacturing Test Flow of Digital Systems

Nicola di Gruttola Giardino;Francesco Angione;Paolo Bernardi;Tommaso Foscale;
2024

Abstract

In the past years, the complexity of Automotive System-on-Chips (SoCs) has risen dramatically, mainly dictated by the increasing application requirements. As the complexity increases, safety standards, such as ISO 26262, impose quality requirements on manufactured devices. Manufactured SoCs go through a manufacturing test flow where, at every step, a set of tests is conducted to verify that the SoCs are manufactured correctly. Although the manufacturing test flow has been stabilized among companies, with the rising complexity of SoCs, the test pace is hard to keep. Consequently, in the last decade, many companies introduced the so-called System-Level Test (SLT) as an additional test step. SLT could be combined with other test steps in order to screen faulty SoCs effectively. Industrial semiconductor testers are available in the market. However, to the best of our knowledge, in the state-of-the-art FPGA-based semiconductor tester, no tester can combine different advanced test strategies, such as advanced functional applications (SLT) and structural tests (scan-based). The proposed FPGA-based Test Equipment aims to overcome the limitations in Research Labs (at universities or in companies), for failure analysis and test-flow prototyping; since an industrial tester, called Automatic Test Equipment (ATE) is expensive and requires physical space. Experimental results show how the hardware is carried out on an FPGA platform with its performance and utilization factor. Meanwhile, the execution time of the software is profiled. Using an industrial Automotive SoC, it shows how the proposed semiconductor tester enables the development of different test strategies.
2024
979-8-3503-6688-4
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2991802